diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 9d8b2f1..9281ceb 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -15,6 +15,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An var privilegeService : PrivilegeService = null object MEMORY_ENABLE extends Stageable(Bool) + object MEMORY_MANAGMENT extends Stageable(Bool) + object MEMORY_WR extends Stageable(Bool) object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits)) object MEMORY_ATOMIC extends Stageable(Bool) @@ -35,12 +37,16 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, - BYPASSABLE_MEMORY_STAGE -> False + BYPASSABLE_MEMORY_STAGE -> False, + MEMORY_WR -> False, + MEMORY_MANAGMENT -> False ) val storeActions = stdActions ++ List( SRC2_CTRL -> Src2CtrlEnum.IMS, - RS2_USE -> True + RS2_USE -> True, + MEMORY_WR -> True, + MEMORY_MANAGMENT -> False ) decoderService.addDefault(MEMORY_ENABLE, False) @@ -56,7 +62,6 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An decoderService.add( key = LR, values = loadActions.filter(_._1 != SRC2_CTRL) ++ Seq( - RS2_USE -> True, SRC2_CTRL -> Src2CtrlEnum.RS, MEMORY_ATOMIC -> True ) @@ -64,7 +69,6 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An decoderService.add( key = SC, values = storeActions.filter(_._1 != SRC2_CTRL) ++ Seq( - SRC2_CTRL -> Src2CtrlEnum.RS, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> False, @@ -76,7 +80,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An def MANAGEMENT = M"-------00000-----101-----0001111" decoderService.add(MANAGEMENT, stdActions ++ List( SRC2_CTRL -> Src2CtrlEnum.RS, - RS2_USE -> True + RS2_USE -> True, + MEMORY_MANAGMENT -> True )) mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(pipeline.memory,memoryTranslatorPortConfig) @@ -119,13 +124,11 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An execute plug new Area { import execute._ - //TODO manage removeIt val size = input(INSTRUCTION)(13 downto 12).asUInt cache.io.cpu.execute.isValid := arbitration.isValid && input(MEMORY_ENABLE) cache.io.cpu.execute.isStuck := arbitration.isStuck -// arbitration.haltIt.setWhen(cache.io.cpu.execute.haltIt) - cache.io.cpu.execute.args.wr := input(INSTRUCTION)(5) + cache.io.cpu.execute.args.wr := input(MEMORY_WR) cache.io.cpu.execute.args.address := input(SRC_ADD).asUInt cache.io.cpu.execute.args.data := size.mux( U(0) -> input(RS2)( 7 downto 0) ## input(RS2)( 7 downto 0) ## input(RS2)(7 downto 0) ## input(RS2)(7 downto 0), @@ -134,11 +137,17 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An ) cache.io.cpu.execute.args.size := size cache.io.cpu.execute.args.forceUncachedAccess := False - cache.io.cpu.execute.args.kind := input(INSTRUCTION)(2) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY + cache.io.cpu.execute.args.kind := input(MEMORY_MANAGMENT) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY cache.io.cpu.execute.args.clean := input(INSTRUCTION)(28) cache.io.cpu.execute.args.invalidate := input(INSTRUCTION)(29) cache.io.cpu.execute.args.way := input(INSTRUCTION)(30) - if(genAtomic) cache.io.cpu.execute.args.isAtomic := input(MEMORY_ATOMIC) + if(genAtomic) { + cache.io.cpu.execute.args.isAtomic := False + when(input(MEMORY_ATOMIC)){ + cache.io.cpu.execute.args.isAtomic := True + cache.io.cpu.execute.args.address := input(SRC1).asUInt + } + } insert(MEMORY_ADDRESS_LOW) := cache.io.cpu.execute.args.address(1 downto 0) } @@ -165,10 +174,10 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An exceptionBus.badAddr := cache.io.cpu.writeBack.badAddr exceptionBus.code.assignDontCare() when(cache.io.cpu.writeBack.illegalAccess || cache.io.cpu.writeBack.accessError){ - exceptionBus.code := (input(INSTRUCTION)(5) ? U(7) | U(5)).resized + exceptionBus.code := (input(MEMORY_WR) ? U(7) | U(5)).resized } when(cache.io.cpu.writeBack.unalignedAccess){ - exceptionBus.code := (input(INSTRUCTION)(5) ? U(6) | U(4)).resized + exceptionBus.code := (input(MEMORY_WR) ? U(6) | U(4)).resized } when(cache.io.cpu.writeBack.mmuMiss){ exceptionBus.code := 13 diff --git a/src/test/cpp/custom/atomic/build/atomic.asm b/src/test/cpp/custom/atomic/build/atomic.asm index e5351c8..56807fa 100644 --- a/src/test/cpp/custom/atomic/build/atomic.asm +++ b/src/test/cpp/custom/atomic/build/atomic.asm @@ -10,35 +10,62 @@ Disassembly of section .crt_section: 8: 06400593 li a1,100 c: 06500613 li a2,101 10: 06600693 li a3,102 - 14: 00d52023 sw a3,0(a0) # 10000000 + 14: 00d52023 sw a3,0(a0) # 10000000 18: 18b5262f sc.w a2,a1,(a0) - 1c: 02060c63 beqz a2,54 - 20: 00052703 lw a4,0(a0) - 24: 02e69863 bne a3,a4,54 - 28: 00200e13 li t3,2 - 2c: 10000537 lui a0,0x10000 - 30: 06400593 li a1,100 - 34: 06500613 li a2,101 - 38: 06600693 li a3,102 - 3c: 00d52023 sw a3,0(a0) # 10000000 - 40: 18b5262f sc.w a2,a1,(a0) - 44: 00060863 beqz a2,54 - 48: 00052703 lw a4,0(a0) - 4c: 00e69463 bne a3,a4,54 - 50: 0100006f j 60 + 1c: 00100713 li a4,1 + 20: 0ae61063 bne a2,a4,c0 + 24: 00052703 lw a4,0(a0) + 28: 08e69c63 bne a3,a4,c0 + 2c: 00200e13 li t3,2 + 30: 10000537 lui a0,0x10000 + 34: 00450513 addi a0,a0,4 # 10000004 + 38: 06700593 li a1,103 + 3c: 06800613 li a2,104 + 40: 06900693 li a3,105 + 44: 00d52023 sw a3,0(a0) + 48: 18b5262f sc.w a2,a1,(a0) + 4c: 00100713 li a4,1 + 50: 06e61863 bne a2,a4,c0 + 54: 00052703 lw a4,0(a0) + 58: 06e69463 bne a3,a4,c0 + 5c: 00300e13 li t3,3 + 60: 10000537 lui a0,0x10000 + 64: 00450513 addi a0,a0,4 # 10000004 + 68: 06700593 li a1,103 + 6c: 06800613 li a2,104 + 70: 06900693 li a3,105 + 74: 18b5262f sc.w a2,a1,(a0) + 78: 00100713 li a4,1 + 7c: 04e61263 bne a2,a4,c0 + 80: 00052703 lw a4,0(a0) + 84: 02e69e63 bne a3,a4,c0 + 88: 00400e13 li t3,4 + 8c: 10000537 lui a0,0x10000 + 90: 00850513 addi a0,a0,8 # 10000008 + 94: 06a00593 li a1,106 + 98: 06b00613 li a2,107 + 9c: 06c00693 li a3,108 + a0: 00d52023 sw a3,0(a0) + a4: 100527af lr.w a5,(a0) + a8: 18b5262f sc.w a2,a1,(a0) + ac: 00d79a63 bne a5,a3,c0 + b0: 00061863 bnez a2,c0 + b4: 00052703 lw a4,0(a0) + b8: 00e59463 bne a1,a4,c0 + bc: 0100006f j cc -00000054 : - 54: f0100137 lui sp,0xf0100 - 58: f2410113 addi sp,sp,-220 # f00fff24 - 5c: 01c12023 sw t3,0(sp) +000000c0 : + c0: f0100137 lui sp,0xf0100 + c4: f2410113 addi sp,sp,-220 # f00fff24 + c8: 01c12023 sw t3,0(sp) -00000060 : - 60: f0100137 lui sp,0xf0100 - 64: f2010113 addi sp,sp,-224 # f00fff20 - 68: 00012023 sw zero,0(sp) - 6c: 00000013 nop - 70: 00000013 nop - 74: 00000013 nop - 78: 00000013 nop - 7c: 00000013 nop - 80: 00000013 nop +000000cc : + cc: f0100137 lui sp,0xf0100 + d0: f2010113 addi sp,sp,-224 # f00fff20 + d4: 00012023 sw zero,0(sp) + d8: 00000013 nop + dc: 00000013 nop + e0: 00000013 nop + e4: 00000013 nop + e8: 00000013 nop + ec: 00000013 nop diff --git a/src/test/cpp/custom/atomic/build/atomic.elf b/src/test/cpp/custom/atomic/build/atomic.elf index 329fd55..1df8609 100755 Binary files a/src/test/cpp/custom/atomic/build/atomic.elf and b/src/test/cpp/custom/atomic/build/atomic.elf differ diff --git a/src/test/cpp/custom/atomic/build/atomic.hex b/src/test/cpp/custom/atomic/build/atomic.hex index 7c19430..f209883 100644 --- a/src/test/cpp/custom/atomic/build/atomic.hex +++ b/src/test/cpp/custom/atomic/build/atomic.hex @@ -1,10 +1,16 @@ :10000000130E100037050010930540061306500626 -:10001000930660062320D5002F26B518630C060230 -:10002000032705006398E602130E20003705001031 -:100030009305400613065006930660062320D5005C -:100040002F26B51863080600032705006394E60011 -:100050006F000001370110F0130141F22320C101AC -:10006000370110F0130101F22320010013000000FA -:100070001300000013000000130000001300000034 -:040080001300000069 +:10001000930660062320D5002F26B518130710007D +:100020006310E60A03270500639CE608130E200010 +:10003000370500101305450093057006130680066A +:10004000930690062320D5002F26B518130710001D +:100050006318E606032705006394E606130E3000D6 +:10006000370500101305450093057006130680063A +:10007000930690062F26B518130710006312E604A6 +:1000800003270500639EE602130E400037050010AB +:10009000130585009305A0061306B0069306C00657 +:1000A0002320D500AF2705102F26B518639AD70057 +:1000B00063180600032705006394E5006F00000144 +:1000C000370110F0130141F22320C101370110F074 +:1000D000130101F2232001001300000013000000AF +:1000E00013000000130000001300000013000000C4 :00000001FF diff --git a/src/test/cpp/custom/atomic/build/atomic.map b/src/test/cpp/custom/atomic/build/atomic.map index 1c5a2c2..af7ef7f 100644 --- a/src/test/cpp/custom/atomic/build/atomic.map +++ b/src/test/cpp/custom/atomic/build/atomic.map @@ -16,15 +16,15 @@ END GROUP LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a 0x0000000000000000 . = 0x0 -.crt_section 0x0000000000000000 0x84 +.crt_section 0x0000000000000000 0xf0 0x0000000000000000 . = ALIGN (0x4) *crt.o(.text) - .text 0x0000000000000000 0x84 build/src/crt.o + .text 0x0000000000000000 0xf0 build/src/crt.o 0x0000000000000000 _start OUTPUT(build/atomic.elf elf32-littleriscv) -.data 0x0000000000000084 0x0 - .data 0x0000000000000084 0x0 build/src/crt.o +.data 0x00000000000000f0 0x0 + .data 0x00000000000000f0 0x0 build/src/crt.o -.bss 0x0000000000000084 0x0 - .bss 0x0000000000000084 0x0 build/src/crt.o +.bss 0x00000000000000f0 0x0 + .bss 0x00000000000000f0 0x0 build/src/crt.o diff --git a/src/test/cpp/custom/atomic/build/atomic.v b/src/test/cpp/custom/atomic/build/atomic.v index f093cc9..207a902 100755 --- a/src/test/cpp/custom/atomic/build/atomic.v +++ b/src/test/cpp/custom/atomic/build/atomic.v @@ -1,10 +1,16 @@ @00000000 13 0E 10 00 37 05 00 10 93 05 40 06 13 06 50 06 -93 06 60 06 23 20 D5 00 2F 26 B5 18 63 0C 06 02 -03 27 05 00 63 98 E6 02 13 0E 20 00 37 05 00 10 -93 05 40 06 13 06 50 06 93 06 60 06 23 20 D5 00 -2F 26 B5 18 63 08 06 00 03 27 05 00 63 94 E6 00 -6F 00 00 01 37 01 10 F0 13 01 41 F2 23 20 C1 01 -37 01 10 F0 13 01 01 F2 23 20 01 00 13 00 00 00 +93 06 60 06 23 20 D5 00 2F 26 B5 18 13 07 10 00 +63 10 E6 0A 03 27 05 00 63 9C E6 08 13 0E 20 00 +37 05 00 10 13 05 45 00 93 05 70 06 13 06 80 06 +93 06 90 06 23 20 D5 00 2F 26 B5 18 13 07 10 00 +63 18 E6 06 03 27 05 00 63 94 E6 06 13 0E 30 00 +37 05 00 10 13 05 45 00 93 05 70 06 13 06 80 06 +93 06 90 06 2F 26 B5 18 13 07 10 00 63 12 E6 04 +03 27 05 00 63 9E E6 02 13 0E 40 00 37 05 00 10 +13 05 85 00 93 05 A0 06 13 06 B0 06 93 06 C0 06 +23 20 D5 00 AF 27 05 10 2F 26 B5 18 63 9A D7 00 +63 18 06 00 03 27 05 00 63 94 E5 00 6F 00 00 01 +37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0 +13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 diff --git a/src/test/cpp/custom/atomic/src/crt.S b/src/test/cpp/custom/atomic/src/crt.S index 105c1e7..9b4a046 100644 --- a/src/test/cpp/custom/atomic/src/crt.S +++ b/src/test/cpp/custom/atomic/src/crt.S @@ -10,23 +10,51 @@ _start: li a3, 102 sw a3, 0(a0) sc.w a2, a1, (a0) - beq a2, x0, fail + li a4, 1 + bne a2, a4, fail lw a4, 0(a0) bne a3, a4, fail -//Test 2 retrying SC on unreserved area should fail and not write memory +//Test 2 SC on another unreserved area should fail and not write memory li x28, 2 - li a0, 0x10000000 - li a1, 100 - li a2, 101 - li a3, 102 + li a0, 0x10000004 + li a1, 103 + li a2, 104 + li a3, 105 sw a3, 0(a0) sc.w a2, a1, (a0) - beq a2, x0, fail + li a4, 1 + bne a2, a4, fail lw a4, 0(a0) bne a3, a4, fail +//Test 3 retrying SC on unreserved area should fail and not write memory + li x28, 3 + li a0, 0x10000004 + li a1, 103 + li a2, 104 + li a3, 105 + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + + +//Test 4 SC on reserved area should pass and should be written write memory + li x28, 4 + li a0, 0x10000008 + li a1, 106 + li a2, 107 + li a3, 108 + sw a3, 0(a0) + lr.w a5, (a0) + sc.w a2, a1, (a0) + bne a5, a3, fail + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail j pass