From 611f2f487fa35a88c4c5113f9454f6dacb4c4c33 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 4 Jan 2018 15:24:00 +0100 Subject: [PATCH] Fix DataCache atomic integration into DBusCachedPlugin Atomic is passing basic tests --- .../vexriscv/plugin/DBusCachedPlugin.scala | 33 ++++--- src/test/cpp/custom/atomic/build/atomic.asm | 85 ++++++++++++------ src/test/cpp/custom/atomic/build/atomic.elf | Bin 4600 -> 4708 bytes src/test/cpp/custom/atomic/build/atomic.hex | 22 +++-- src/test/cpp/custom/atomic/build/atomic.map | 12 +-- src/test/cpp/custom/atomic/build/atomic.v | 20 +++-- src/test/cpp/custom/atomic/src/crt.S | 42 +++++++-- 7 files changed, 145 insertions(+), 69 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 9d8b2f1..9281ceb 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -15,6 +15,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An var privilegeService : PrivilegeService = null object MEMORY_ENABLE extends Stageable(Bool) + object MEMORY_MANAGMENT extends Stageable(Bool) + object MEMORY_WR extends Stageable(Bool) object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits)) object MEMORY_ATOMIC extends Stageable(Bool) @@ -35,12 +37,16 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, - BYPASSABLE_MEMORY_STAGE -> False + BYPASSABLE_MEMORY_STAGE -> False, + MEMORY_WR -> False, + MEMORY_MANAGMENT -> False ) val storeActions = stdActions ++ List( SRC2_CTRL -> Src2CtrlEnum.IMS, - RS2_USE -> True + RS2_USE -> True, + MEMORY_WR -> True, + MEMORY_MANAGMENT -> False ) decoderService.addDefault(MEMORY_ENABLE, False) @@ -56,7 +62,6 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An decoderService.add( key = LR, values = loadActions.filter(_._1 != SRC2_CTRL) ++ Seq( - RS2_USE -> True, SRC2_CTRL -> Src2CtrlEnum.RS, MEMORY_ATOMIC -> True ) @@ -64,7 +69,6 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An decoderService.add( key = SC, values = storeActions.filter(_._1 != SRC2_CTRL) ++ Seq( - SRC2_CTRL -> Src2CtrlEnum.RS, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> False, @@ -76,7 +80,8 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An def MANAGEMENT = M"-------00000-----101-----0001111" decoderService.add(MANAGEMENT, stdActions ++ List( SRC2_CTRL -> Src2CtrlEnum.RS, - RS2_USE -> True + RS2_USE -> True, + MEMORY_MANAGMENT -> True )) mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(pipeline.memory,memoryTranslatorPortConfig) @@ -119,13 +124,11 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An execute plug new Area { import execute._ - //TODO manage removeIt val size = input(INSTRUCTION)(13 downto 12).asUInt cache.io.cpu.execute.isValid := arbitration.isValid && input(MEMORY_ENABLE) cache.io.cpu.execute.isStuck := arbitration.isStuck -// arbitration.haltIt.setWhen(cache.io.cpu.execute.haltIt) - cache.io.cpu.execute.args.wr := input(INSTRUCTION)(5) + cache.io.cpu.execute.args.wr := input(MEMORY_WR) cache.io.cpu.execute.args.address := input(SRC_ADD).asUInt cache.io.cpu.execute.args.data := size.mux( U(0) -> input(RS2)( 7 downto 0) ## input(RS2)( 7 downto 0) ## input(RS2)(7 downto 0) ## input(RS2)(7 downto 0), @@ -134,11 +137,17 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An ) cache.io.cpu.execute.args.size := size cache.io.cpu.execute.args.forceUncachedAccess := False - cache.io.cpu.execute.args.kind := input(INSTRUCTION)(2) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY + cache.io.cpu.execute.args.kind := input(MEMORY_MANAGMENT) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY cache.io.cpu.execute.args.clean := input(INSTRUCTION)(28) cache.io.cpu.execute.args.invalidate := input(INSTRUCTION)(29) cache.io.cpu.execute.args.way := input(INSTRUCTION)(30) - if(genAtomic) cache.io.cpu.execute.args.isAtomic := input(MEMORY_ATOMIC) + if(genAtomic) { + cache.io.cpu.execute.args.isAtomic := False + when(input(MEMORY_ATOMIC)){ + cache.io.cpu.execute.args.isAtomic := True + cache.io.cpu.execute.args.address := input(SRC1).asUInt + } + } insert(MEMORY_ADDRESS_LOW) := cache.io.cpu.execute.args.address(1 downto 0) } @@ -165,10 +174,10 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An exceptionBus.badAddr := cache.io.cpu.writeBack.badAddr exceptionBus.code.assignDontCare() when(cache.io.cpu.writeBack.illegalAccess || cache.io.cpu.writeBack.accessError){ - exceptionBus.code := (input(INSTRUCTION)(5) ? U(7) | U(5)).resized + exceptionBus.code := (input(MEMORY_WR) ? U(7) | U(5)).resized } when(cache.io.cpu.writeBack.unalignedAccess){ - exceptionBus.code := (input(INSTRUCTION)(5) ? U(6) | U(4)).resized + exceptionBus.code := (input(MEMORY_WR) ? U(6) | U(4)).resized } when(cache.io.cpu.writeBack.mmuMiss){ exceptionBus.code := 13 diff --git a/src/test/cpp/custom/atomic/build/atomic.asm b/src/test/cpp/custom/atomic/build/atomic.asm index e5351c8..56807fa 100644 --- a/src/test/cpp/custom/atomic/build/atomic.asm +++ b/src/test/cpp/custom/atomic/build/atomic.asm @@ -10,35 +10,62 @@ Disassembly of section .crt_section: 8: 06400593 li a1,100 c: 06500613 li a2,101 10: 06600693 li a3,102 - 14: 00d52023 sw a3,0(a0) # 10000000 + 14: 00d52023 sw a3,0(a0) # 10000000 18: 18b5262f sc.w a2,a1,(a0) - 1c: 02060c63 beqz a2,54 - 20: 00052703 lw a4,0(a0) - 24: 02e69863 bne a3,a4,54 - 28: 00200e13 li t3,2 - 2c: 10000537 lui a0,0x10000 - 30: 06400593 li a1,100 - 34: 06500613 li a2,101 - 38: 06600693 li a3,102 - 3c: 00d52023 sw a3,0(a0) # 10000000 - 40: 18b5262f sc.w a2,a1,(a0) - 44: 00060863 beqz a2,54 - 48: 00052703 lw a4,0(a0) - 4c: 00e69463 bne a3,a4,54 - 50: 0100006f j 60 + 1c: 00100713 li a4,1 + 20: 0ae61063 bne a2,a4,c0 + 24: 00052703 lw a4,0(a0) + 28: 08e69c63 bne a3,a4,c0 + 2c: 00200e13 li t3,2 + 30: 10000537 lui a0,0x10000 + 34: 00450513 addi a0,a0,4 # 10000004 + 38: 06700593 li a1,103 + 3c: 06800613 li a2,104 + 40: 06900693 li a3,105 + 44: 00d52023 sw a3,0(a0) + 48: 18b5262f sc.w a2,a1,(a0) + 4c: 00100713 li a4,1 + 50: 06e61863 bne a2,a4,c0 + 54: 00052703 lw a4,0(a0) + 58: 06e69463 bne a3,a4,c0 + 5c: 00300e13 li t3,3 + 60: 10000537 lui a0,0x10000 + 64: 00450513 addi a0,a0,4 # 10000004 + 68: 06700593 li a1,103 + 6c: 06800613 li a2,104 + 70: 06900693 li a3,105 + 74: 18b5262f sc.w a2,a1,(a0) + 78: 00100713 li a4,1 + 7c: 04e61263 bne a2,a4,c0 + 80: 00052703 lw a4,0(a0) + 84: 02e69e63 bne a3,a4,c0 + 88: 00400e13 li t3,4 + 8c: 10000537 lui a0,0x10000 + 90: 00850513 addi a0,a0,8 # 10000008 + 94: 06a00593 li a1,106 + 98: 06b00613 li a2,107 + 9c: 06c00693 li a3,108 + a0: 00d52023 sw a3,0(a0) + a4: 100527af lr.w a5,(a0) + a8: 18b5262f sc.w a2,a1,(a0) + ac: 00d79a63 bne a5,a3,c0 + b0: 00061863 bnez a2,c0 + b4: 00052703 lw a4,0(a0) + b8: 00e59463 bne a1,a4,c0 + bc: 0100006f j cc -00000054 : - 54: f0100137 lui sp,0xf0100 - 58: f2410113 addi sp,sp,-220 # f00fff24 - 5c: 01c12023 sw t3,0(sp) +000000c0 : + c0: f0100137 lui sp,0xf0100 + c4: f2410113 addi sp,sp,-220 # f00fff24 + c8: 01c12023 sw t3,0(sp) -00000060 : - 60: f0100137 lui sp,0xf0100 - 64: f2010113 addi sp,sp,-224 # f00fff20 - 68: 00012023 sw zero,0(sp) - 6c: 00000013 nop - 70: 00000013 nop - 74: 00000013 nop - 78: 00000013 nop - 7c: 00000013 nop - 80: 00000013 nop +000000cc : + cc: f0100137 lui sp,0xf0100 + d0: f2010113 addi sp,sp,-224 # f00fff20 + d4: 00012023 sw zero,0(sp) + d8: 00000013 nop + dc: 00000013 nop + e0: 00000013 nop + e4: 00000013 nop + e8: 00000013 nop + ec: 00000013 nop diff --git a/src/test/cpp/custom/atomic/build/atomic.elf b/src/test/cpp/custom/atomic/build/atomic.elf index 329fd558a723230f26fffbaaec2e8cdb59955b63..1df8609e02c976a6449ee59535b9850aa3b54397 100755 GIT binary patch delta 233 zcmeyN{6uAf0^^*Cips1X7#J8nZ1lX$UoXrqz>qBPjEh;Fl_7b~GY(-s1qO3g1_5DK zSBA-~1#H4>4Q!LyCa@_hTxHN#+bRK8FY$~GtbWQfHeo&ktm@%vg`Tm1)y{jyB+Tak zRoewIzzGq8w13Gr<45!G6fF+oeKes3}QgWnaL*w e7BhaBoGYjdBqs{0GX)4v-X*BUSTy;epf~_+s5ndj delta 131 zcmaE&@hJjgxuUn3&aB8Ior_V-n_5U@&K85SYyBz$VNV zz&4pJflXQADuce-R*7T|HU_Y|DbFVF7RVF~0h#~-j0|ExM#5xM!NrU%lWz(t1IfRF a>a0%$7#Nf$2MP&Kwh