From 6142b04603bdbd8896b1e0733e3b1caab7523482 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Sat, 26 May 2018 11:43:16 +0200
Subject: [PATCH] Move HexTools into Spinal

---
 src/main/scala/spinal/lib/misc/HexTools.scala | 41 +++++++++++++++++++
 src/main/scala/vexriscv/demo/Briey.scala      |  9 ++--
 .../scala/vexriscv/demo/MuraxUtiles.scala     | 39 +-----------------
 3 files changed, 47 insertions(+), 42 deletions(-)
 create mode 100644 src/main/scala/spinal/lib/misc/HexTools.scala

diff --git a/src/main/scala/spinal/lib/misc/HexTools.scala b/src/main/scala/spinal/lib/misc/HexTools.scala
new file mode 100644
index 0000000..c3bd67c
--- /dev/null
+++ b/src/main/scala/spinal/lib/misc/HexTools.scala
@@ -0,0 +1,41 @@
+package spinal.lib.misc
+
+import spinal.core._
+
+object HexTools{
+  def readHexFile(path : String, callback : (Int, Int) => Unit, hexOffset : Int = 0): Unit ={
+    import scala.io.Source
+    def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
+
+    var offset = 0
+    for (line <- Source.fromFile(path).getLines) {
+      if (line.charAt(0) == ':'){
+        val byteCount = hToI(line, 1, 2)
+        val nextAddr = hToI(line, 3, 4) + offset
+        val key = hToI(line, 7, 2)
+        key match {
+          case 0 =>
+            for(i <- 0 until byteCount){
+              callback(nextAddr + i - hexOffset, hToI(line, 9 + i * 2, 2))
+            }
+          case 2 =>
+            offset = hToI(line, 9, 4) << 4
+          case 4 =>
+            offset = hToI(line, 9, 4) << 16
+          case 3 =>
+          case 5 =>
+          case 1 =>
+        }
+      }
+    }
+  }
+
+  def initRam[T <: Data](ram : Mem[T], onChipRamHexFile : String, hexOffset : BigInt): Unit ={
+    val initContent = Array.fill[BigInt](ram.wordCount)(0)
+    HexTools.readHexFile(onChipRamHexFile,(address,data) => {
+      val addressWithoutOffset = (address - hexOffset).toInt
+      initContent(addressWithoutOffset >> 2) |= BigInt(data) << ((addressWithoutOffset & 3)*8)
+    })
+    ram.initBigInt(initContent)
+  }
+}
\ No newline at end of file
diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
index 451fdd9..bfb3862 100644
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@@ -9,13 +9,14 @@ import spinal.lib._
 import spinal.lib.bus.amba3.apb._
 import spinal.lib.bus.amba4.axi._
 import spinal.lib.com.jtag.Jtag
-import spinal.lib.com.uart.{Uart, UartCtrlGenerics, UartCtrlMemoryMappedConfig, Apb3UartCtrl}
+import spinal.lib.com.uart.{Apb3UartCtrl, Uart, UartCtrlGenerics, UartCtrlMemoryMappedConfig}
 import spinal.lib.graphic.RgbConfig
-import spinal.lib.graphic.vga.{Vga, Axi4VgaCtrlGenerics, Axi4VgaCtrl}
+import spinal.lib.graphic.vga.{Axi4VgaCtrl, Axi4VgaCtrlGenerics, Vga}
 import spinal.lib.io.TriStateArray
 import spinal.lib.memory.sdram._
-import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
-import spinal.lib.system.debugger.{SystemDebugger, JtagBridge, JtagAxi4SharedDebugger, SystemDebuggerConfig}
+import spinal.lib.misc.HexTools
+import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
+import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, JtagBridge, SystemDebugger, SystemDebuggerConfig}
 
 import scala.collection.mutable.ArrayBuffer
 
diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala
index 3a32a74..8aaf8a0 100644
--- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala
+++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala
@@ -3,7 +3,7 @@ package vexriscv.demo
 import spinal.core._
 import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory}
 import spinal.lib.bus.misc.SizeMapping
-import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
+import spinal.lib.misc.{HexTools, InterruptCtrl, Prescaler, Timer}
 import spinal.lib._
 import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus}
 
@@ -73,43 +73,6 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
   io.dBus.rsp.error := False
 }
 
-object HexTools{
-  def readHexFile(path : String, callback : (Int, Int) => Unit, offset : Int = 0): Unit ={
-    import scala.io.Source
-    def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
-
-    var offset = 0
-    for (line <- Source.fromFile(path).getLines) {
-      if (line.charAt(0) == ':'){
-        val byteCount = hToI(line, 1, 2)
-        val nextAddr = hToI(line, 3, 4) + offset
-        val key = hToI(line, 7, 2)
-        key match {
-          case 0 =>
-            for(i <- 0 until byteCount){
-              callback(nextAddr + i + offset, hToI(line, 9 + i * 2, 2))
-            }
-          case 2 =>
-            offset = hToI(line, 9, 4) << 4
-          case 4 =>
-            offset = hToI(line, 9, 4) << 16
-          case 3 =>
-          case 5 =>
-          case 1 =>
-        }
-      }
-    }
-  }
-
-  def initRam[T <: Data](ram : Mem[T], onChipRamHexFile : String, ramOffset : BigInt): Unit ={
-    val initContent = Array.fill[BigInt](ram.wordCount)(0)
-    HexTools.readHexFile(onChipRamHexFile,(address,data) => {
-      val addressWithoutOffset = (address - ramOffset).toInt
-      initContent(addressWithoutOffset >> 2) |= BigInt(data) << ((addressWithoutOffset & 3)*8)
-    })
-    ram.initBigInt(initContent)
-  }
-}
 
 class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
   val io = new Bundle{