From 61d25e931e45dc00a5e497a7e4c7619e20ac1c7f Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Sat, 13 Apr 2019 10:44:06 +0200
Subject: [PATCH] #60 Add sim error message on RVC instruction without RVC
 capabilities

---
 src/test/cpp/regression/main.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index d42f56c..518f30c 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -958,6 +958,7 @@ public:
 			}
 		} else {
 			#ifndef COMPRESSED
+			cout << "ERROR : RiscvGolden got a RVC instruction while the CPU isn't RVC ready" << endl;
 	        ilegalInstruction(); return;
 			#endif
 			switch((iBits(0, 2) << 3) + iBits(13, 3)){