diff --git a/src/main/scala/vexriscv/demo/GenSecure.scala b/src/main/scala/vexriscv/demo/GenSecure.scala index 2835b44..e4da3eb 100644 --- a/src/main/scala/vexriscv/demo/GenSecure.scala +++ b/src/main/scala/vexriscv/demo/GenSecure.scala @@ -41,6 +41,7 @@ object GenSecure extends App { ), new PmpPlugin( regions = 16, + granularity = 256, ioRange = _(31 downto 28) === 0xf ), new DecoderSimplePlugin( diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 98fc113..eb538ef 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -32,11 +32,7 @@ object CsrAccess { object NONE extends CsrAccess } -object CsrPlugin { - object IS_CSR extends Stageable(Bool) - object CSR_WRITE_OPCODE extends Stageable(Bool) - object CSR_READ_OPCODE extends Stageable(Bool) -} + case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int) case class CsrPluginConfig( @@ -348,9 +344,16 @@ case class CsrDuringWrite(doThat :() => Unit) case class CsrDuringRead(doThat :() => Unit) case class CsrDuring(doThat :() => Unit) case class CsrOnRead(doThat : () => Unit) -case class CsrIgnoreIllegal() + + case class CsrMapping() extends CsrInterface{ val mapping = mutable.LinkedHashMap[Int,ArrayBuffer[Any]]() + val always = ArrayBuffer[Any]() + val readDataSignal, readDataInit, writeDataSignal = Bits(32 bits) + val allowCsrSignal = False + val hazardFree = Bool() + + readDataSignal := readDataInit def addMappingAt(address : Int,that : Any) = mapping.getOrElseUpdate(address,new ArrayBuffer[Any]) += that override def r(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrRead(that,bitOffset)) override def w(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrWrite(that,bitOffset)) @@ -361,7 +364,12 @@ case class CsrMapping() extends CsrInterface{ override def during(csrAddress: Int)(body: => Unit): Unit = addMappingAt(csrAddress, CsrDuring(() => body)) override def onRead(csrAddress: Int)(body: => Unit): Unit = addMappingAt(csrAddress, CsrOnRead(() => {body})) override def duringAny(): Bool = ??? - override def ignoreIllegal(csrAddress: Int) : Unit = addMappingAt(csrAddress, CsrIgnoreIllegal()) + override def duringAnyWrite(body: => Unit) : Unit = always += CsrDuringRead(() => body) + override def duringAnyRead(body: => Unit) : Unit = always += CsrDuringWrite(() => body) + override def readData() = readDataSignal + override def writeData() = writeDataSignal + override def allowCsr() = allowCsrSignal := True + override def isHazardFree() = hazardFree } @@ -378,7 +386,10 @@ trait CsrInterface{ r(csrAddress,bitOffset,that) w(csrAddress,bitOffset,that) } - def ignoreIllegal(csrAddress : Int) : Unit + def duringAnyWrite(body: => Unit) : Unit //Called all the durration of a Csr write instruction in the execute stage + def duringAnyRead(body: => Unit) : Unit //same than above for read + def allowCsr() : Unit //In case your csr do not use the regular API with csrAddress but is implemented using "side channels", you can call that if the current csr is implemented + def isHazardFree() : Bool // You should not have any side effect nor use readData() until this return True def r2w(csrAddress : Int, bitOffset : Int,that : Data): Unit @@ -403,6 +414,9 @@ trait CsrInterface{ } ret } + + def readData() : Bits //Return the 32 bits internal signal of the CsrPlugin for you to override (if you want) + def writeData() : Bits //Return the 32 bits value that the CsrPlugin want to write in the CSR (depend on readData combinatorialy) } @@ -416,7 +430,6 @@ trait IWake{ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface with IWake{ import config._ import CsrAccess._ - import CsrPlugin._ assert(!(wfiGenAsNop && wfiGenAsWait)) @@ -460,12 +473,16 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } object ENV_CTRL extends Stageable(EnvCtrlEnum()) + object IS_CSR extends Stageable(Bool) + object CSR_WRITE_OPCODE extends Stageable(Bool) + object CSR_READ_OPCODE extends Stageable(Bool) object PIPELINED_CSR_READ extends Stageable(Bits(32 bits)) var allowInterrupts : Bool = null var allowException : Bool = null + var allowEbreakException : Bool = null - val csrMapping = new CsrMapping() + var csrMapping : CsrMapping = null //Print CSR mapping def printCsr() { @@ -498,11 +515,18 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep override def duringRead(csrAddress: Int)(body: => Unit): Unit = csrMapping.duringRead(csrAddress)(body) override def during(csrAddress: Int)(body: => Unit): Unit = csrMapping.during(csrAddress)(body) override def duringAny(): Bool = pipeline.execute.arbitration.isValid && pipeline.execute.input(IS_CSR) - override def ignoreIllegal(csrAddress: Int): Unit = csrMapping.ignoreIllegal(csrAddress) + override def duringAnyWrite(body: => Unit) = csrMapping.duringAnyWrite(body) + override def duringAnyRead(body: => Unit) = csrMapping.duringAnyRead(body) + override def allowCsr() = csrMapping.allowCsr() + override def readData() = csrMapping.readData() + override def writeData() = csrMapping.writeData() + override def isHazardFree() = csrMapping.isHazardFree() override def setup(pipeline: VexRiscv): Unit = { import pipeline.config._ + csrMapping = new CsrMapping() + inWfi = False.addTag(Verilator.public) thirdPartyWake = False @@ -573,6 +597,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep allowInterrupts = True allowException = True + allowEbreakException = True for (i <- interruptSpecs) i.cond = i.cond.pull() @@ -585,6 +610,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep def inhibateInterrupts() : Unit = allowInterrupts := False def inhibateException() : Unit = allowException := False + def inhibateEbreakException() : Unit = allowEbreakException := False override def isUser() : Bool = privilege === 0 override def isSupervisor(): Bool = privilege === 1 @@ -959,9 +985,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep targetPrivilege := exceptionPortCtrl.exceptionTargetPrivilege } - val trapCause = CombInit(interrupt.code) + val trapCause = CombInit(interrupt.code.resize(trapCodeWidth)) if(exceptionPortCtrl != null) when( hadException){ - trapCause := exceptionPortCtrl.exceptionContext.code + trapCause := exceptionPortCtrl.exceptionContext.code.resized } val xtvec = Xtvec().assignDontCare() @@ -1053,6 +1079,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep insert(CSR_READ_OPCODE) := input(INSTRUCTION)(13 downto 7) =/= B"0100000" } + execute plug new Area{ import execute._ //Manage WFI instructions @@ -1104,7 +1131,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } - if(ebreakGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.EBREAK){ + if(ebreakGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.EBREAK && allowEbreakException){ selfException.valid := True selfException.code := 3 } @@ -1112,17 +1139,19 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val imm = IMM(input(INSTRUCTION)) def writeSrc = input(SRC1) - val readData = Bits(32 bits) + def readData = csrMapping.readDataSignal + def writeData = csrMapping.writeDataSignal val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) val writeEnable = writeInstruction && !arbitration.isStuck val readEnable = readInstruction && !arbitration.isStuck + csrMapping.hazardFree := !blockedBySideEffects val readToWriteData = CombInit(readData) - val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( + writeData := (if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( False -> writeSrc, True -> Mux(input(INSTRUCTION)(12), readToWriteData & ~writeSrc, readToWriteData | writeSrc) - ) + )) when(arbitration.isValid && input(IS_CSR)) { if(!pipelineCsrRead) output(REGFILE_WRITE_DATA) := readData @@ -1134,6 +1163,12 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep memory.output(REGFILE_WRITE_DATA) := memory.input(PIPELINED_CSR_READ) } } +// +// Component.current.rework{ +// when(arbitration.isFiring && input(IS_CSR)) { +// memory.input(REGFILE_WRITE_DATA).getDrivingReg := readData +// } +// } //Translation of the csrMapping into real logic val csrAddress = input(INSTRUCTION)(csrRange) @@ -1141,8 +1176,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep def doJobs(jobs : ArrayBuffer[Any]): Unit ={ val withWrite = jobs.exists(j => j.isInstanceOf[CsrWrite] || j.isInstanceOf[CsrOnWrite] || j.isInstanceOf[CsrDuringWrite]) val withRead = jobs.exists(j => j.isInstanceOf[CsrRead] || j.isInstanceOf[CsrOnRead]) - val ignoreIllegal = jobs.exists(j => j.isInstanceOf[CsrIgnoreIllegal]) - if(withRead && withWrite | ignoreIllegal) { + if(withRead && withWrite) { illegalAccess := False } else { if (withWrite) illegalAccess.clearWhen(input(CSR_WRITE_OPCODE)) @@ -1182,13 +1216,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep csrOhDecoder match { case false => { - readData := 0 + csrMapping.readDataInit := 0 switch(csrAddress) { for ((address, jobs) <- csrMapping.mapping) { is(address) { doJobs(jobs) for (element <- jobs) element match { - case element: CsrRead if element.that.getBitsWidth != 0 => readData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits + case element: CsrRead if element.that.getBitsWidth != 0 => csrMapping.readDataInit (element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits case _ => } } @@ -1218,7 +1252,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep readDatas += masked } } - readData := readDatas.reduceBalancedTree(_ | _) + csrMapping.readDataInit := readDatas.reduceBalancedTree(_ | _) for ((address, jobs) <- csrMapping.mapping) { when(oh(address)){ doJobsOverride(jobs) @@ -1227,6 +1261,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } } + csrMapping.always.foreach { + case element : CsrDuringWrite => when(writeInstruction){element.doThat()} + case element : CsrDuringRead => when(readInstruction){element.doThat()} + } + + illegalAccess clearWhen(csrMapping.allowCsrSignal) + when(privilege < csrAddress(9 downto 8).asUInt){ illegalAccess := True readInstruction := False diff --git a/src/main/scala/vexriscv/plugin/PmpPlugin.scala b/src/main/scala/vexriscv/plugin/PmpPlugin.scala index 1f49453..efd1a52 100644 --- a/src/main/scala/vexriscv/plugin/PmpPlugin.scala +++ b/src/main/scala/vexriscv/plugin/PmpPlugin.scala @@ -7,7 +7,6 @@ package vexriscv.plugin import vexriscv.{VexRiscv, _} -import vexriscv.plugin.CsrPlugin.{_} import vexriscv.plugin.MemoryTranslatorPort.{_} import spinal.core._ import spinal.lib._ @@ -79,42 +78,26 @@ trait Pmp { def lBit = 7 } -class PmpSetter() extends Component with Pmp { +class PmpSetter(grain : Int) extends Component with Pmp { val io = new Bundle { - val a = in Bits(2 bits) val addr = in UInt(xlen bits) - val prevHi = in UInt(30 bits) - val boundLo, boundHi = out UInt(30 bits) + val base, mask = out UInt(xlen - grain bits) } - val shifted = io.addr(29 downto 0) - io.boundLo := shifted - io.boundHi := shifted - - switch (io.a) { - is (TOR) { - io.boundLo := io.prevHi - } - is (NA4) { - io.boundHi := shifted + 1 - } - is (NAPOT) { - val mask = io.addr & ~(io.addr + 1) - val boundLo = (io.addr ^ mask)(29 downto 0) - io.boundLo := boundLo - io.boundHi := boundLo + ((mask + 1) |<< 3)(29 downto 0) - } - } + val ones = io.addr & ~(io.addr + 1) + io.base := io.addr(xlen - 1 - grain downto 0) ^ ones(xlen - 1 - grain downto 0) + io.mask := ~ones(xlen - grain downto 1) } case class ProtectedMemoryTranslatorPort(bus : MemoryTranslatorBus) -class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTranslator with Pmp { - assert(regions % 4 == 0) - assert(regions <= 16) +class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTranslator with Pmp { + assert(regions % 4 == 0 & regions <= 16) + assert(granularity >= 8) var setter : PmpSetter = null var dPort, iPort : ProtectedMemoryTranslatorPort = null + val grain = log2Up(granularity) - 1 override def newTranslationPort(priority : Int, args : Any): MemoryTranslatorBus = { val port = ProtectedMemoryTranslatorPort(MemoryTranslatorBus(new MemoryTranslatorBusParameter(0, 0))) @@ -126,7 +109,7 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] } override def setup(pipeline: VexRiscv): Unit = { - setter = new PmpSetter() + setter = new PmpSetter(grain) } override def build(pipeline: VexRiscv): Unit = { @@ -137,56 +120,76 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] val csrService = pipeline.service(classOf[CsrInterface]) val privilegeService = pipeline.service(classOf[PrivilegeService]) - for (i <- 0x3a0 to 0x3a3) csrService.ignoreIllegal(i) - for (i <- 0x3b0 to 0x3bf) csrService.ignoreIllegal(i) - val pmpaddr = Mem(UInt(xlen bits), regions) val pmpcfg = Reg(Bits(8 * regions bits)) init(0) - val boundLo, boundHi = Mem(UInt(30 bits), regions) + val base, mask = Mem(UInt(xlen - grain bits), regions) val cfgRegion = pmpcfg.subdivideIn(8 bits) val cfgRegister = pmpcfg.subdivideIn(xlen bits) val lockMask = Reg(Bits(4 bits)) init(B"4'0") - object IS_PMP_CFG extends Stageable(Bool) - object IS_PMP_ADDR extends Stageable(Bool) + object PMPCFG extends Stageable(Bool) + object PMPADDR extends Stageable(Bool) decode plug new Area { import decode._ - insert(IS_PMP_CFG) := input(INSTRUCTION)(31 downto 24) === 0x3a - insert(IS_PMP_ADDR) := input(INSTRUCTION)(31 downto 24) === 0x3b + insert(PMPCFG) := input(INSTRUCTION)(31 downto 24) === 0x3a + insert(PMPADDR) := input(INSTRUCTION)(31 downto 24) === 0x3b } execute plug new Area { import execute._ + val mask0 = mask(U"4'x0") + val mask1 = mask(U"4'x1") + val mask2 = mask(U"4'x2") + val mask3 = mask(U"4'x3") + val mask4 = mask(U"4'x4") + val mask5 = mask(U"4'x5") + val mask6 = mask(U"4'x6") + val mask7 = mask(U"4'x7") + val mask8 = mask(U"4'x8") + val mask9 = mask(U"4'x9") + val mask10 = mask(U"4'xa") + val mask11 = mask(U"4'xb") + val mask12 = mask(U"4'xc") + val mask13 = mask(U"4'xd") + val mask14 = mask(U"4'xe") + val mask15 = mask(U"4'xf") + val base0 = base(U"4'x0") + val base1 = base(U"4'x1") + val base2 = base(U"4'x2") + val base3 = base(U"4'x3") + val base4 = base(U"4'x4") + val base5 = base(U"4'x5") + val base6 = base(U"4'x6") + val base7 = base(U"4'x7") + val base8 = base(U"4'x8") + val base9 = base(U"4'x9") + val base10 = base(U"4'xa") + val base11 = base(U"4'xb") + val base12 = base(U"4'xc") + val base13 = base(U"4'xd") + val base14 = base(U"4'xe") + val base15 = base(U"4'xf") + val csrAddress = input(INSTRUCTION)(csrRange) - val accessAddr = input(IS_PMP_ADDR) - val accessCfg = input(IS_PMP_CFG) - val accessAny = (accessAddr | accessCfg) & privilegeService.isMachine() - val pmpWrite = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) & accessAny - val pmpRead = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) & accessAny val pmpIndex = csrAddress(log2Up(regions) - 1 downto 0).asUInt val pmpSelect = pmpIndex(log2Up(regions) - 3 downto 0) + val writeData = csrService.writeData() + + val enable = RegInit(False) + for (i <- 0 until regions) { + csrService.onRead(0x3b0 + i) {csrService.readData().assignFromBits(cfgRegister(pmpSelect)) } + csrService.onWrite(0x3b0 + i) { enable := True } + } + for (i <- 0 until (regions / 4)) { + csrService.onRead(0x3a0 + i) { csrService.readData() := pmpaddr.readAsync(pmpIndex).asBits } + csrService.onWrite(0x3a0 + i) { enable := True } + } - val readAddr = pmpaddr.readAsync(pmpIndex).asBits - val readCfg = cfgRegister(pmpSelect) - val readToWrite = Mux(accessCfg, readCfg, readAddr) - val writeSrc = input(SRC1) - val writeData = input(INSTRUCTION)(13).mux( - False -> writeSrc, - True -> Mux( - input(INSTRUCTION)(12), - readToWrite & ~writeSrc, - readToWrite | writeSrc - ) - ) - val writer = new Area { - when (accessCfg) { - when (pmpRead) { - output(REGFILE_WRITE_DATA).assignFromBits(readCfg) - } - when (pmpWrite) { + when (enable & csrService.isHazardFree()) { + when (input(PMPCFG)) { switch(pmpSelect) { for (i <- 0 until (regions / 4)) { is(i) { @@ -197,29 +200,19 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] lockMask(j / 8) := locked when (~locked) { pmpcfg(bitRange).assignFromBits(overwrite) - if (j != 0 || i != 0) { - when (overwrite(lBit) & overwrite(aBits) === TOR) { - pmpcfg(j + xlen * i - 1) := True - } - } } } } } } } - }.elsewhen (accessAddr) { - when (pmpRead) { - output(REGFILE_WRITE_DATA) := readAddr - } } val locked = cfgRegion(pmpIndex)(lBit) - pmpaddr.write(pmpIndex, writeData.asUInt, ~locked & pmpWrite & accessAddr) + pmpaddr.write(pmpIndex, writeData.asUInt, ~locked & input(PMPADDR) & enable & csrService.isHazardFree()) } val controller = new StateMachine { val counter = Reg(UInt(log2Up(regions) bits)) init(0) - val enable = RegInit(False) val stateIdle : State = new State with EntryPoint { onEntry { @@ -227,15 +220,12 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] enable := False counter := 0 } - onExit { - enable := True - arbitration.haltItself := True - } + onExit (arbitration.haltItself := True) whenIsActive { - when (pmpWrite) { - when (accessCfg) { + when (enable & csrService.isHazardFree()) { + when (input(PMPCFG)) { goto(stateCfg) - }.elsewhen (accessAddr) { + }.elsewhen (input(PMPADDR)) { goto(stateAddr) } } @@ -256,21 +246,12 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] val stateAddr : State = new State { onEntry (counter := pmpIndex) - whenIsActive { - counter := counter + 1 - when (counter === (pmpIndex + 1) | counter === 0) { - goto(stateIdle) - } otherwise { - arbitration.haltItself := True - } - } + whenIsActive (goto(stateIdle)) } - when (accessCfg) { - setter.io.a := writeData.subdivideIn(8 bits)(counter(1 downto 0))(aBits) + when (input(PMPCFG)) { setter.io.addr := pmpaddr(counter) } otherwise { - setter.io.a := cfgRegion(counter)(aBits) when (counter === pmpIndex) { setter.io.addr := writeData.asUInt } otherwise { @@ -278,17 +259,11 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] } } - when (counter === 0) { - setter.io.prevHi := 0 - } otherwise { - setter.io.prevHi := boundHi(counter - 1) - } - - when (enable & - ((accessCfg & ~lockMask(counter(1 downto 0))) | - (accessAddr & ~cfgRegion(counter)(lBit)))) { - boundLo(counter) := setter.io.boundLo - boundHi(counter) := setter.io.boundHi + when (enable & csrService.isHazardFree() & + ((input(PMPCFG) & ~lockMask(counter(1 downto 0))) | + (input(PMPADDR) & ~cfgRegion(counter)(lBit)))) { + base(counter) := setter.io.base + mask(counter) := setter.io.mask } } } @@ -296,10 +271,8 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] pipeline plug new Area { def getHits(address : UInt) = { (0 until regions).map(i => - address >= boundLo(U(i, log2Up(regions) bits)) & - address < boundHi(U(i, log2Up(regions) bits)) & - (cfgRegion(i)(lBit) | ~privilegeService.isMachine()) & - cfgRegion(i)(aBits) =/= 0 + ((address & mask(U(i, log2Up(regions) bits))) === base(U(i, log2Up(regions) bits))) & + (cfgRegion(i)(lBit) | ~privilegeService.isMachine()) & cfgRegion(i)(aBits) === NAPOT ) } @@ -313,15 +286,14 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] dPort.bus.rsp.allowExecute := False dPort.bus.busy := False - val hits = getHits(address(31 downto 2)) + val hits = getHits(address(31 downto grain)) when(~hits.orR) { dPort.bus.rsp.allowRead := privilegeService.isMachine() dPort.bus.rsp.allowWrite := privilegeService.isMachine() } otherwise { - val oneHot = OHMasking.first(hits) - dPort.bus.rsp.allowRead := MuxOH(oneHot, cfgRegion.map(cfg => cfg(rBit))) - dPort.bus.rsp.allowWrite := MuxOH(oneHot, cfgRegion.map(cfg => cfg(wBit))) + dPort.bus.rsp.allowRead := (hits zip cfgRegion).map({ case (i, cfg) => i & cfg(rBit) }).orR + dPort.bus.rsp.allowWrite := (hits zip cfgRegion).map({ case (i, cfg) => i & cfg(wBit) }).orR } } @@ -336,13 +308,12 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] iPort.bus.rsp.allowWrite := False iPort.bus.busy := False - val hits = getHits(address(31 downto 2)) + val hits = getHits(address(31 downto grain)) when(~hits.orR) { iPort.bus.rsp.allowExecute := privilegeService.isMachine() } otherwise { - val oneHot = OHMasking.first(hits) - iPort.bus.rsp.allowExecute := MuxOH(oneHot, cfgRegion.map(cfg => cfg(xBit))) + iPort.bus.rsp.allowExecute := (hits zip cfgRegion).map({ case (i, cfg) => i & cfg(xBit) }).orR } } } diff --git a/src/test/cpp/raw/pmp/build/pmp.asm b/src/test/cpp/raw/pmp/build/pmp.asm index ef3f280..6db26c3 100644 --- a/src/test/cpp/raw/pmp/build/pmp.asm +++ b/src/test/cpp/raw/pmp/build/pmp.asm @@ -22,273 +22,271 @@ Disassembly of section .crt_section: 80000024 : 80000024: 00000e13 li t3,0 80000028: 00000f17 auipc t5,0x0 -8000002c: 3a4f0f13 addi t5,t5,932 # 800003cc +8000002c: 39cf0f13 addi t5,t5,924 # 800003c4 80000030: 800000b7 lui ra,0x80000 80000034: 80008237 lui tp,0x80008 80000038: deadc137 lui sp,0xdeadc -8000003c: eef10113 addi sp,sp,-273 # deadbeef -80000040: 0020a023 sw sp,0(ra) # 80000000 -80000044: 00222023 sw sp,0(tp) # 80008000 +8000003c: eef10113 addi sp,sp,-273 # deadbeef +80000040: 0020a023 sw sp,0(ra) # 80000000 +80000044: 00222023 sw sp,0(tp) # 80008000 80000048: 0000a183 lw gp,0(ra) -8000004c: 38311063 bne sp,gp,800003cc +8000004c: 36311c63 bne sp,gp,800003c4 80000050: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> -80000054: 36311c63 bne sp,gp,800003cc +80000054: 36311863 bne sp,gp,800003c4 80000058: 071202b7 lui t0,0x7120 8000005c: 3a029073 csrw pmpcfg0,t0 80000060: 3a002373 csrr t1,pmpcfg0 -80000064: 36629463 bne t0,t1,800003cc -80000068: 191f02b7 lui t0,0x191f0 -8000006c: 30428293 addi t0,t0,772 # 191f0304 <_start-0x66e0fcfc> -80000070: 3a129073 csrw pmpcfg1,t0 -80000074: 000f12b7 lui t0,0xf1 -80000078: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6> -8000007c: 3a229073 csrw pmpcfg2,t0 -80000080: 0f1e22b7 lui t0,0xf1e2 -80000084: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700> -80000088: 3a329073 csrw pmpcfg3,t0 -8000008c: 200002b7 lui t0,0x20000 -80000090: 3b029073 csrw pmpaddr0,t0 -80000094: 3b002373 csrr t1,pmpaddr0 -80000098: 32629a63 bne t0,t1,800003cc -8000009c: fff00293 li t0,-1 -800000a0: 3b129073 csrw pmpaddr1,t0 -800000a4: 200022b7 lui t0,0x20002 -800000a8: 3b229073 csrw pmpaddr2,t0 -800000ac: 200042b7 lui t0,0x20004 -800000b0: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> -800000b4: 3b329073 csrw pmpaddr3,t0 -800000b8: 200042b7 lui t0,0x20004 -800000bc: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> -800000c0: 3b429073 csrw pmpaddr4,t0 -800000c4: 200042b7 lui t0,0x20004 -800000c8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> -800000cc: 3b529073 csrw pmpaddr5,t0 -800000d0: 200022b7 lui t0,0x20002 -800000d4: fff28293 addi t0,t0,-1 # 20001fff <_start-0x5fffe001> -800000d8: 3b629073 csrw pmpaddr6,t0 -800000dc: 200062b7 lui t0,0x20006 -800000e0: fff28293 addi t0,t0,-1 # 20005fff <_start-0x5fffa001> -800000e4: 3b729073 csrw pmpaddr7,t0 -800000e8: 200d02b7 lui t0,0x200d0 -800000ec: 3b829073 csrw pmpaddr8,t0 -800000f0: 200e02b7 lui t0,0x200e0 -800000f4: 3b929073 csrw pmpaddr9,t0 -800000f8: fff00293 li t0,-1 -800000fc: 3ba29073 csrw pmpaddr10,t0 +80000064: 191f02b7 lui t0,0x191f0 +80000068: 30428293 addi t0,t0,772 # 191f0304 <_start-0x66e0fcfc> +8000006c: 3a129073 csrw pmpcfg1,t0 +80000070: 000f12b7 lui t0,0xf1 +80000074: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6> +80000078: 3a229073 csrw pmpcfg2,t0 +8000007c: 0f1e22b7 lui t0,0xf1e2 +80000080: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700> +80000084: 3a329073 csrw pmpcfg3,t0 +80000088: 200002b7 lui t0,0x20000 +8000008c: 3b029073 csrw pmpaddr0,t0 +80000090: 3b002373 csrr t1,pmpaddr0 +80000094: fff00293 li t0,-1 +80000098: 3b129073 csrw pmpaddr1,t0 +8000009c: 200022b7 lui t0,0x20002 +800000a0: 3b229073 csrw pmpaddr2,t0 +800000a4: 200042b7 lui t0,0x20004 +800000a8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000ac: 3b329073 csrw pmpaddr3,t0 +800000b0: 200042b7 lui t0,0x20004 +800000b4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000b8: 3b429073 csrw pmpaddr4,t0 +800000bc: 200042b7 lui t0,0x20004 +800000c0: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000c4: 3b529073 csrw pmpaddr5,t0 +800000c8: 200022b7 lui t0,0x20002 +800000cc: fff28293 addi t0,t0,-1 # 20001fff <_start-0x5fffe001> +800000d0: 3b629073 csrw pmpaddr6,t0 +800000d4: 200062b7 lui t0,0x20006 +800000d8: fff28293 addi t0,t0,-1 # 20005fff <_start-0x5fffa001> +800000dc: 3b729073 csrw pmpaddr7,t0 +800000e0: 200d02b7 lui t0,0x200d0 +800000e4: 3b829073 csrw pmpaddr8,t0 +800000e8: 200e02b7 lui t0,0x200e0 +800000ec: 3b929073 csrw pmpaddr9,t0 +800000f0: fff00293 li t0,-1 +800000f4: 3ba29073 csrw pmpaddr10,t0 +800000f8: 00000293 li t0,0 +800000fc: 3bb29073 csrw pmpaddr11,t0 80000100: 00000293 li t0,0 -80000104: 3bb29073 csrw pmpaddr11,t0 +80000104: 3bc29073 csrw pmpaddr12,t0 80000108: 00000293 li t0,0 -8000010c: 3bc29073 csrw pmpaddr12,t0 +8000010c: 3bd29073 csrw pmpaddr13,t0 80000110: 00000293 li t0,0 -80000114: 3bd29073 csrw pmpaddr13,t0 +80000114: 3be29073 csrw pmpaddr14,t0 80000118: 00000293 li t0,0 -8000011c: 3be29073 csrw pmpaddr14,t0 -80000120: 00000293 li t0,0 -80000124: 3bf29073 csrw pmpaddr15,t0 -80000128: 00c10137 lui sp,0xc10 -8000012c: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012> -80000130: 0020a023 sw sp,0(ra) -80000134: 00222023 sw sp,0(tp) # 0 <_start-0x80000000> -80000138: 0000a183 lw gp,0(ra) -8000013c: 28311863 bne sp,gp,800003cc -80000140: 00000193 li gp,0 -80000144: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> -80000148: 28311263 bne sp,gp,800003cc +8000011c: 3bf29073 csrw pmpaddr15,t0 +80000120: 00c10137 lui sp,0xc10 +80000124: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012> +80000128: 0020a023 sw sp,0(ra) +8000012c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000> +80000130: 0000a183 lw gp,0(ra) +80000134: 28311863 bne sp,gp,800003c4 +80000138: 00000193 li gp,0 +8000013c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> +80000140: 28311263 bne sp,gp,800003c4 -8000014c : -8000014c: 00100e13 li t3,1 -80000150: 00000f17 auipc t5,0x0 -80000154: 27cf0f13 addi t5,t5,636 # 800003cc -80000158: 079212b7 lui t0,0x7921 -8000015c: 80828293 addi t0,t0,-2040 # 7920808 <_start-0x786df7f8> -80000160: 3a029073 csrw pmpcfg0,t0 -80000164: 3a002373 csrr t1,pmpcfg0 -80000168: 26629263 bne t0,t1,800003cc -8000016c: 800080b7 lui ra,0x80008 -80000170: deadc137 lui sp,0xdeadc -80000174: eef10113 addi sp,sp,-273 # deadbeef -80000178: 0020a023 sw sp,0(ra) # 80008000 -8000017c: 00000f17 auipc t5,0x0 -80000180: 010f0f13 addi t5,t5,16 # 8000018c -80000184: 0000a183 lw gp,0(ra) -80000188: 2440006f j 800003cc +80000144 : +80000144: 00100e13 li t3,1 +80000148: 00000f17 auipc t5,0x0 +8000014c: 27cf0f13 addi t5,t5,636 # 800003c4 +80000150: 079212b7 lui t0,0x7921 +80000154: 80828293 addi t0,t0,-2040 # 7920808 <_start-0x786df7f8> +80000158: 3a029073 csrw pmpcfg0,t0 +8000015c: 3a002373 csrr t1,pmpcfg0 +80000160: 26629263 bne t0,t1,800003c4 +80000164: 800080b7 lui ra,0x80008 +80000168: deadc137 lui sp,0xdeadc +8000016c: eef10113 addi sp,sp,-273 # deadbeef +80000170: 0020a023 sw sp,0(ra) # 80008000 +80000174: 00000f17 auipc t5,0x0 +80000178: 010f0f13 addi t5,t5,16 # 80000184 +8000017c: 0000a183 lw gp,0(ra) +80000180: 2440006f j 800003c4 -8000018c : -8000018c: 00200e13 li t3,2 -80000190: 00000f17 auipc t5,0x0 -80000194: 23cf0f13 addi t5,t5,572 # 800003cc -80000198: 071202b7 lui t0,0x7120 -8000019c: 3a029073 csrw pmpcfg0,t0 -800001a0: 3a002373 csrr t1,pmpcfg0 -800001a4: 22628463 beq t0,t1,800003cc -800001a8: 200042b7 lui t0,0x20004 -800001ac: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> -800001b0: 3b305073 csrwi pmpaddr3,0 -800001b4: 3b302373 csrr t1,pmpaddr3 -800001b8: 20031a63 bnez t1,800003cc -800001bc: 20628863 beq t0,t1,800003cc -800001c0: 200022b7 lui t0,0x20002 -800001c4: 3b205073 csrwi pmpaddr2,0 -800001c8: 3b202373 csrr t1,pmpaddr2 -800001cc: 20030063 beqz t1,800003cc -800001d0: 1e629e63 bne t0,t1,800003cc -800001d4: 800080b7 lui ra,0x80008 -800001d8: deadc137 lui sp,0xdeadc -800001dc: eef10113 addi sp,sp,-273 # deadbeef -800001e0: 0020a023 sw sp,0(ra) # 80008000 -800001e4: 00000f17 auipc t5,0x0 -800001e8: 010f0f13 addi t5,t5,16 # 800001f4 -800001ec: 0000a183 lw gp,0(ra) -800001f0: 1dc0006f j 800003cc +80000184 : +80000184: 00200e13 li t3,2 +80000188: 00000f17 auipc t5,0x0 +8000018c: 23cf0f13 addi t5,t5,572 # 800003c4 +80000190: 071202b7 lui t0,0x7120 +80000194: 3a029073 csrw pmpcfg0,t0 +80000198: 3a002373 csrr t1,pmpcfg0 +8000019c: 22628463 beq t0,t1,800003c4 +800001a0: 200042b7 lui t0,0x20004 +800001a4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800001a8: 3b305073 csrwi pmpaddr3,0 +800001ac: 3b302373 csrr t1,pmpaddr3 +800001b0: 20031a63 bnez t1,800003c4 +800001b4: 20628863 beq t0,t1,800003c4 +800001b8: 200022b7 lui t0,0x20002 +800001bc: 3b205073 csrwi pmpaddr2,0 +800001c0: 3b202373 csrr t1,pmpaddr2 +800001c4: 20030063 beqz t1,800003c4 +800001c8: 1e629e63 bne t0,t1,800003c4 +800001cc: 800080b7 lui ra,0x80008 +800001d0: deadc137 lui sp,0xdeadc +800001d4: eef10113 addi sp,sp,-273 # deadbeef +800001d8: 0020a023 sw sp,0(ra) # 80008000 +800001dc: 00000f17 auipc t5,0x0 +800001e0: 010f0f13 addi t5,t5,16 # 800001ec +800001e4: 0000a183 lw gp,0(ra) +800001e8: 1dc0006f j 800003c4 -800001f4 : -800001f4: 00300e13 li t3,3 -800001f8: 00000f17 auipc t5,0x0 -800001fc: 1d4f0f13 addi t5,t5,468 # 800003cc -80000200: 00ff02b7 lui t0,0xff0 -80000204: 3b32a073 csrs pmpaddr3,t0 -80000208: 3b302373 csrr t1,pmpaddr3 -8000020c: 1c629063 bne t0,t1,800003cc -80000210: 0ff00293 li t0,255 -80000214: 3b32a073 csrs pmpaddr3,t0 -80000218: 3b302373 csrr t1,pmpaddr3 -8000021c: 00ff02b7 lui t0,0xff0 -80000220: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> -80000224: 1a629463 bne t0,t1,800003cc -80000228: 00ff02b7 lui t0,0xff0 -8000022c: 3b32b073 csrc pmpaddr3,t0 -80000230: 3b302373 csrr t1,pmpaddr3 -80000234: 0ff00293 li t0,255 -80000238: 18629a63 bne t0,t1,800003cc -8000023c: 00ff02b7 lui t0,0xff0 -80000240: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> -80000244: 3a02b073 csrc pmpcfg0,t0 -80000248: 3a002373 csrr t1,pmpcfg0 -8000024c: 079202b7 lui t0,0x7920 -80000250: 16629e63 bne t0,t1,800003cc -80000254: 00ff02b7 lui t0,0xff0 -80000258: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9> -8000025c: 3a02a073 csrs pmpcfg0,t0 -80000260: 3a002373 csrr t1,pmpcfg0 -80000264: 079202b7 lui t0,0x7920 -80000268: 70728293 addi t0,t0,1799 # 7920707 <_start-0x786df8f9> -8000026c: 16629063 bne t0,t1,800003cc +800001ec : +800001ec: 00300e13 li t3,3 +800001f0: 00000f17 auipc t5,0x0 +800001f4: 1d4f0f13 addi t5,t5,468 # 800003c4 +800001f8: 00ff02b7 lui t0,0xff0 +800001fc: 3b32a073 csrs pmpaddr3,t0 +80000200: 3b302373 csrr t1,pmpaddr3 +80000204: 1c629063 bne t0,t1,800003c4 +80000208: 0ff00293 li t0,255 +8000020c: 3b32a073 csrs pmpaddr3,t0 +80000210: 3b302373 csrr t1,pmpaddr3 +80000214: 00ff02b7 lui t0,0xff0 +80000218: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> +8000021c: 1a629463 bne t0,t1,800003c4 +80000220: 00ff02b7 lui t0,0xff0 +80000224: 3b32b073 csrc pmpaddr3,t0 +80000228: 3b302373 csrr t1,pmpaddr3 +8000022c: 0ff00293 li t0,255 +80000230: 18629a63 bne t0,t1,800003c4 +80000234: 00ff02b7 lui t0,0xff0 +80000238: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> +8000023c: 3a02b073 csrc pmpcfg0,t0 +80000240: 3a002373 csrr t1,pmpcfg0 +80000244: 079202b7 lui t0,0x7920 +80000248: 16629e63 bne t0,t1,800003c4 +8000024c: 00ff02b7 lui t0,0xff0 +80000250: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9> +80000254: 3a02a073 csrs pmpcfg0,t0 +80000258: 3a002373 csrr t1,pmpcfg0 +8000025c: 079202b7 lui t0,0x7920 +80000260: 70728293 addi t0,t0,1799 # 7920707 <_start-0x786df8f9> +80000264: 16629063 bne t0,t1,800003c4 -80000270 : -80000270: 00400e13 li t3,4 -80000274: 00000f17 auipc t5,0x0 -80000278: 158f0f13 addi t5,t5,344 # 800003cc -8000027c: 00000117 auipc sp,0x0 -80000280: 01010113 addi sp,sp,16 # 8000028c -80000284: 34111073 csrw mepc,sp -80000288: 30200073 mret +80000268 : +80000268: 00400e13 li t3,4 +8000026c: 00000f17 auipc t5,0x0 +80000270: 158f0f13 addi t5,t5,344 # 800003c4 +80000274: 00000117 auipc sp,0x0 +80000278: 01010113 addi sp,sp,16 # 80000284 +8000027c: 34111073 csrw mepc,sp +80000280: 30200073 mret -8000028c : -8000028c: 00500e13 li t3,5 -80000290: 00000f17 auipc t5,0x0 -80000294: 13cf0f13 addi t5,t5,316 # 800003cc -80000298: deadc137 lui sp,0xdeadc -8000029c: eef10113 addi sp,sp,-273 # deadbeef -800002a0: 800080b7 lui ra,0x80008 -800002a4: 0020a023 sw sp,0(ra) # 80008000 -800002a8: 00000f17 auipc t5,0x0 -800002ac: 010f0f13 addi t5,t5,16 # 800002b8 -800002b0: 0000a183 lw gp,0(ra) -800002b4: 1180006f j 800003cc +80000284 : +80000284: 00500e13 li t3,5 +80000288: 00000f17 auipc t5,0x0 +8000028c: 13cf0f13 addi t5,t5,316 # 800003c4 +80000290: deadc137 lui sp,0xdeadc +80000294: eef10113 addi sp,sp,-273 # deadbeef +80000298: 800080b7 lui ra,0x80008 +8000029c: 0020a023 sw sp,0(ra) # 80008000 +800002a0: 00000f17 auipc t5,0x0 +800002a4: 010f0f13 addi t5,t5,16 # 800002b0 +800002a8: 0000a183 lw gp,0(ra) +800002ac: 1180006f j 800003c4 -800002b8 : -800002b8: 00600e13 li t3,6 -800002bc: 00000f17 auipc t5,0x0 -800002c0: 110f0f13 addi t5,t5,272 # 800003cc -800002c4: deadc137 lui sp,0xdeadc -800002c8: eef10113 addi sp,sp,-273 # deadbeef -800002cc: 800000b7 lui ra,0x80000 -800002d0: 0020a023 sw sp,0(ra) # 80000000 -800002d4: 0000a183 lw gp,0(ra) -800002d8: 0e311a63 bne sp,gp,800003cc +800002b0 : +800002b0: 00600e13 li t3,6 +800002b4: 00000f17 auipc t5,0x0 +800002b8: 110f0f13 addi t5,t5,272 # 800003c4 +800002bc: deadc137 lui sp,0xdeadc +800002c0: eef10113 addi sp,sp,-273 # deadbeef +800002c4: 800000b7 lui ra,0x80000 +800002c8: 0020a023 sw sp,0(ra) # 80000000 +800002cc: 0000a183 lw gp,0(ra) +800002d0: 0e311a63 bne sp,gp,800003c4 -800002dc : -800002dc: 00700e13 li t3,7 -800002e0: 00000f17 auipc t5,0x0 -800002e4: 0ecf0f13 addi t5,t5,236 # 800003cc -800002e8: 800400b7 lui ra,0x80040 -800002ec: 0000a183 lw gp,0(ra) # 80040000 -800002f0: 00000f17 auipc t5,0x0 -800002f4: 010f0f13 addi t5,t5,16 # 80000300 -800002f8: 0030a023 sw gp,0(ra) -800002fc: 0d00006f j 800003cc +800002d4 : +800002d4: 00700e13 li t3,7 +800002d8: 00000f17 auipc t5,0x0 +800002dc: 0ecf0f13 addi t5,t5,236 # 800003c4 +800002e0: 800400b7 lui ra,0x80040 +800002e4: 0000a183 lw gp,0(ra) # 80040000 +800002e8: 00000f17 auipc t5,0x0 +800002ec: 010f0f13 addi t5,t5,16 # 800002f8 +800002f0: 0030a023 sw gp,0(ra) +800002f4: 0d00006f j 800003c4 -80000300 : -80000300: 00800e13 li t3,8 -80000304: 00000f17 auipc t5,0x0 -80000308: 0c8f0f13 addi t5,t5,200 # 800003cc -8000030c: deadc137 lui sp,0xdeadc -80000310: eef10113 addi sp,sp,-273 # deadbeef -80000314: 803400b7 lui ra,0x80340 -80000318: ff808093 addi ra,ra,-8 # 8033fff8 -8000031c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000> -80000320: 00000f17 auipc t5,0x0 -80000324: 010f0f13 addi t5,t5,16 # 80000330 -80000328: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> -8000032c: 0a00006f j 800003cc +800002f8 : +800002f8: 00800e13 li t3,8 +800002fc: 00000f17 auipc t5,0x0 +80000300: 0c8f0f13 addi t5,t5,200 # 800003c4 +80000304: deadc137 lui sp,0xdeadc +80000308: eef10113 addi sp,sp,-273 # deadbeef +8000030c: 803400b7 lui ra,0x80340 +80000310: ff808093 addi ra,ra,-8 # 8033fff8 +80000314: 00222023 sw sp,0(tp) # 0 <_start-0x80000000> +80000318: 00000f17 auipc t5,0x0 +8000031c: 010f0f13 addi t5,t5,16 # 80000328 +80000320: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> +80000324: 0a00006f j 800003c4 -80000330 : -80000330: 00900e13 li t3,9 -80000334: 00000f17 auipc t5,0x0 -80000338: 098f0f13 addi t5,t5,152 # 800003cc -8000033c: 803800b7 lui ra,0x80380 -80000340: ff808093 addi ra,ra,-8 # 8037fff8 -80000344: 0000a183 lw gp,0(ra) -80000348: 00000f17 auipc t5,0x0 -8000034c: 010f0f13 addi t5,t5,16 # 80000358 -80000350: 0030a023 sw gp,0(ra) -80000354: 0780006f j 800003cc +80000328 : +80000328: 00900e13 li t3,9 +8000032c: 00000f17 auipc t5,0x0 +80000330: 098f0f13 addi t5,t5,152 # 800003c4 +80000334: 803800b7 lui ra,0x80380 +80000338: ff808093 addi ra,ra,-8 # 8037fff8 +8000033c: 0000a183 lw gp,0(ra) +80000340: 00000f17 auipc t5,0x0 +80000344: 010f0f13 addi t5,t5,16 # 80000350 +80000348: 0030a023 sw gp,0(ra) +8000034c: 0780006f j 800003c4 -80000358 : -80000358: 00a00e13 li t3,10 -8000035c: 00000f17 auipc t5,0x0 -80000360: 014f0f13 addi t5,t5,20 # 80000370 -80000364: 00100493 li s1,1 -80000368: 3a305073 csrwi pmpcfg3,0 -8000036c: 0600006f j 800003cc +80000350 : +80000350: 00a00e13 li t3,10 +80000354: 00000f17 auipc t5,0x0 +80000358: 014f0f13 addi t5,t5,20 # 80000368 +8000035c: 00100493 li s1,1 +80000360: 3a305073 csrwi pmpcfg3,0 +80000364: 0600006f j 800003c4 -80000370 : -80000370: 00a00e13 li t3,10 -80000374: 0f1e22b7 lui t0,0xf1e2 -80000378: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700> -8000037c: 3a302373 csrr t1,pmpcfg3 -80000380: 04629663 bne t0,t1,800003cc +80000368 : +80000368: 00a00e13 li t3,10 +8000036c: 0f1e22b7 lui t0,0xf1e2 +80000370: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700> +80000374: 3a302373 csrr t1,pmpcfg3 +80000378: 04629663 bne t0,t1,800003c4 -80000384 : -80000384: 00b00e13 li t3,11 -80000388: 00000f17 auipc t5,0x0 -8000038c: 044f0f13 addi t5,t5,68 # 800003cc -80000390: 00000493 li s1,0 -80000394: 00000117 auipc sp,0x0 -80000398: 01010113 addi sp,sp,16 # 800003a4 -8000039c: 34111073 csrw mepc,sp -800003a0: 30200073 mret +8000037c : +8000037c: 00b00e13 li t3,11 +80000380: 00000f17 auipc t5,0x0 +80000384: 044f0f13 addi t5,t5,68 # 800003c4 +80000388: 00000493 li s1,0 +8000038c: 00000117 auipc sp,0x0 +80000390: 01010113 addi sp,sp,16 # 8000039c +80000394: 34111073 csrw mepc,sp +80000398: 30200073 mret -800003a4 : -800003a4: 00b00e13 li t3,11 -800003a8: 00000f17 auipc t5,0x0 -800003ac: 014f0f13 addi t5,t5,20 # 800003bc -800003b0: 00100493 li s1,1 -800003b4: 3ba05073 csrwi pmpaddr10,0 -800003b8: 0140006f j 800003cc +8000039c : +8000039c: 00b00e13 li t3,11 +800003a0: 00000f17 auipc t5,0x0 +800003a4: 014f0f13 addi t5,t5,20 # 800003b4 +800003a8: 00100493 li s1,1 +800003ac: 3ba05073 csrwi pmpaddr10,0 +800003b0: 0140006f j 800003c4 -800003bc : -800003bc: 00b00e13 li t3,11 -800003c0: fff00293 li t0,-1 -800003c4: 3ba02373 csrr t1,pmpaddr10 -800003c8: 00628863 beq t0,t1,800003d8 +800003b4 : +800003b4: 00b00e13 li t3,11 +800003b8: fff00293 li t0,-1 +800003bc: 3ba02373 csrr t1,pmpaddr10 +800003c0: 00628863 beq t0,t1,800003d0 -800003cc : -800003cc: f0100137 lui sp,0xf0100 -800003d0: f2410113 addi sp,sp,-220 # f00fff24 -800003d4: 01c12023 sw t3,0(sp) +800003c4 : +800003c4: f0100137 lui sp,0xf0100 +800003c8: f2410113 addi sp,sp,-220 # f00fff24 +800003cc: 01c12023 sw t3,0(sp) -800003d8 : -800003d8: f0100137 lui sp,0xf0100 -800003dc: f2010113 addi sp,sp,-224 # f00fff20 -800003e0: 00012023 sw zero,0(sp) +800003d0 : +800003d0: f0100137 lui sp,0xf0100 +800003d4: f2010113 addi sp,sp,-224 # f00fff20 +800003d8: 00012023 sw zero,0(sp) diff --git a/src/test/cpp/raw/pmp/build/pmp.elf b/src/test/cpp/raw/pmp/build/pmp.elf index 26fc85b..93342d0 100755 Binary files a/src/test/cpp/raw/pmp/build/pmp.elf and b/src/test/cpp/raw/pmp/build/pmp.elf differ diff --git a/src/test/cpp/raw/pmp/build/pmp.hex b/src/test/cpp/raw/pmp/build/pmp.hex index 0672169..2ad2696 100644 --- a/src/test/cpp/raw/pmp/build/pmp.hex +++ b/src/test/cpp/raw/pmp/build/pmp.hex @@ -1,66 +1,65 @@ :0200000480007A :10000000930400009700000093800001739050302B :100010006F00400173101F3463940400730020309C -:1000200067000F00130E0000170F0000130F4F3A68 +:1000200067000F00130E0000170F0000130FCF39E9 :10003000B70000803782008037C1ADDE1301F1EEDA -:1000400023A020002320220083A100006310313868 -:1000500083210200631C3136B70212077390023A03 -:100060007323003A63946236B7021F1993824230B9 -:100070007390123AB7120F009382A2907390223AB3 -:10008000B7221E0F938202907390323AB70200207B -:100090007390023B7323003B639A62329302F0FF3A -:1000A0007390123BB72200207390223BB74200208E -:1000B0009382F2FF7390323BB74200209382F2FFAB -:1000C0007390423BB74200209382F2FF7390523B01 -:1000D000B72200209382F2FF7390623BB762002048 -:1000E0009382F2FF7390723BB7020D207390823BB4 -:1000F000B7020E207390923B9302F0FF7390A23BE5 -:10010000930200007390B23B930200007390C23BD5 -:10011000930200007390D23B930200007390E23B85 -:10012000930200007390F23B3701C1001301E1FE1E -:1001300023A020002320220083A10000631831287F -:10014000930100008321020063123128130E100076 -:10015000170F0000130FCF27B712920793828280E8 -:100160007390023A7323003A63926226B78000804C -:1001700037C1ADDE1301F1EE23A02000170F000000 -:10018000130F0F0183A100006F004024130E200005 -:10019000170F0000130FCF23B70212077390023A14 -:1001A0007323003A63846222B74200209382F2FFF5 -:1001B0007350303B7323303B631A03206388622003 -:1001C000B72200207350203B7323203B63000320A1 -:1001D000639E621EB780008037C1ADDE1301F1EE71 -:1001E00023A02000170F0000130F0F0183A10000B0 -:1001F0006F00C01D130E3000170F0000130F4F1DAE -:10020000B702FF0073A0323B7323303B6390621C44 -:100210009302F00F73A0323B7323303BB702FF0011 -:100220009382F20F6394621AB702FF0073B0323BFD -:100230007323303B9302F00F639A6218B702FF00FA -:100240009382F20F73B0023A7323003AB702920717 -:10025000639E6216B702FF009382727073A0023A27 -:100260007323003AB702920793827270639062160A -:10027000130E4000170F0000130F8F151701000019 -:10028000130101017310113473002030130E50005C -:10029000170F0000130FCF1337C1ADDE1301F1EEBE -:1002A000B780008023A02000170F0000130F0F015C -:1002B00083A100006F008011130E6000170F000073 -:1002C000130F0F1137C1ADDE1301F1EEB70000803F -:1002D00023A0200083A10000631A310E130E7000CA -:1002E000170F0000130FCF0EB700048083A100008A -:1002F000170F0000130F0F0123A030006F00000D37 -:10030000130E8000170F0000130F8F0C37C1ADDEE6 -:100310001301F1EEB7003480938080FF2320220088 -:10032000170F0000130F0F01832102006F00000A56 -:10033000130E9000170F0000130F8F09B7003880BD -:10034000938080FF83A10000170F0000130F0F019F -:1003500023A030006F008007130EA000170F0000CD -:10036000130F4F01930410007350303A6F000006D2 -:10037000130EA000B7221E0F938202907323303A0F -:1003800063966204130EB000170F0000130F4F04A2 -:1003900093040000170100001301010173101134D0 -:1003A00073002030130EB000170F0000130F4F0121 -:1003B000930410007350A03B6F004001130EB00077 -:1003C0009302F0FF7323A03B63886200370110F0B3 -:1003D000130141F22320C101370110F0130101F292 -:0403E00023200100D5 +:1000400023A020002320220083A10000631C31365E +:100050008321020063183136B70212077390023A07 +:100060007323003AB7021F19938242307390123AF9 +:10007000B7120F009382A2907390223AB7221E0FFC +:10008000938202907390323AB70200207390023B41 +:100090007323003B9302F0FF7390123BB7220020C2 +:1000A0007390223BB74200209382F2FF7390323B61 +:1000B000B74200209382F2FF7390423BB742002088 +:1000C0009382F2FF7390523BB72200209382F2FF9B +:1000D0007390623BB76200209382F2FF7390723B91 +:1000E000B7020D207390823BB7020E207390923BB3 +:1000F0009302F0FF7390A23B930200007390B23B17 +:10010000930200007390C23B930200007390D23BB5 +:10011000930200007390E23B930200007390F23B65 +:100120003701C1001301E1FE23A02000232022009B +:1001300083A100006318312893010000832102008D +:1001400063123128130E1000170F0000130FCF2772 +:10015000B7129207938282807390023A7323003A17 +:1001600063926226B780008037C1ADDE1301F1EEE5 +:1001700023A02000170F0000130F0F0183A1000020 +:100180006F004024130E2000170F0000130FCF2321 +:10019000B70212077390023A7323003A6384622213 +:1001A000B74200209382F2FF7350303B7323303B01 +:1001B000631A032063886220B72200207350203B1B +:1001C0007323203B63000320639E621EB780008080 +:1001D00037C1ADDE1301F1EE23A02000170F0000A0 +:1001E000130F0F0183A100006F00C01D130E30001C +:1001F000170F0000130F4F1DB702FF0073A0323B13 +:100200007323303B6390621C9302F00F73A0323B68 +:100210007323303BB702FF009382F20F6394621A9C +:10022000B702FF0073B0323B7323303B9302F00FF1 +:10023000639A6218B702FF009382F20F73B0023A1A +:100240007323003AB7029207639E6216B702FF005B +:100250009382727073A0023A7323003AB702920736 +:100260009382727063906216130E4000170F0000A5 +:10027000130F8F15170100001301010173101134C2 +:1002800073002030130E5000170F0000130FCF1310 +:1002900037C1ADDE1301F1EEB780008023A020004E +:1002A000170F0000130F0F0183A100006F008011D2 +:1002B000130E6000170F0000130F0F1137C1ADDED2 +:1002C0001301F1EEB700008023A0200083A10000FD +:1002D000631A310E130E7000170F0000130FCF0EAC +:1002E000B700048083A10000170F0000130F0F0157 +:1002F00023A030006F00000D130E8000170F0000C8 +:10030000130F8F0C37C1ADDE1301F1EEB70034804F +:10031000938080FF23202200170F0000130F0F018E +:10032000832102006F00000A130E9000170F0000D7 +:10033000130F8F09B7003880938080FF83A10000DE +:10034000170F0000130F0F0123A030006F0080076C +:10035000130EA000170F0000130F4F01930410009D +:100360007350303A6F000006130EA000B7221E0F24 +:10037000938202907323303A63966204130EB000A6 +:10038000170F0000130F4F04930400001701000023 +:10039000130101017310113473002030130EB000EB +:1003A000170F0000130F4F01930410007350A03B70 +:1003B0006F004001130EB0009302F0FF7323A03BC7 +:1003C00063886200370110F0130141F22320C1015C +:0C03D000370110F0130101F2232001009E :040000058000000077 :00000001FF diff --git a/src/test/cpp/raw/pmp/build/pmp.map b/src/test/cpp/raw/pmp/build/pmp.map index 0e76f88..fd0c6b0 100644 --- a/src/test/cpp/raw/pmp/build/pmp.map +++ b/src/test/cpp/raw/pmp/build/pmp.map @@ -15,19 +15,19 @@ LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unk END GROUP LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a -.crt_section 0x0000000080000000 0x3e4 +.crt_section 0x0000000080000000 0x3dc 0x0000000080000000 . = ALIGN (0x4) *crt.o(.text) - .text 0x0000000080000000 0x3e4 build/src/crt.o + .text 0x0000000080000000 0x3dc build/src/crt.o 0x0000000080000000 _start 0x0000000080000014 trap OUTPUT(build/pmp.elf elf32-littleriscv) -.data 0x00000000800003e4 0x0 - .data 0x00000000800003e4 0x0 build/src/crt.o +.data 0x00000000800003dc 0x0 + .data 0x00000000800003dc 0x0 build/src/crt.o -.bss 0x00000000800003e4 0x0 - .bss 0x00000000800003e4 0x0 build/src/crt.o +.bss 0x00000000800003dc 0x0 + .bss 0x00000000800003dc 0x0 build/src/crt.o .riscv.attributes 0x0000000000000000 0x1a