diff --git a/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala b/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
index 6bcd6cb..fee8dee 100644
--- a/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
@@ -9,12 +9,16 @@ import scala.collection.mutable.ArrayBuffer
 
 
 object KeepAttribute{
-  object syn_keep extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
+  object syn_keep_verilog extends AttributeFlag("synthesis syn_keep = 1", COMMENT_ATTRIBUTE){
     override def isLanguageReady(language: Language) : Boolean = language == Language.VERILOG || language == Language.SYSTEM_VERILOG
   }
+
+  object syn_keep_vhdl extends AttributeFlag("syn_keep"){
+    override def isLanguageReady(language: Language) : Boolean = language == Language.VHDL
+  }
   object keep extends AttributeFlag("keep")
 
-  def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep)
+  def apply[T <: Data](that : T) = that.addAttribute(keep).addAttribute(syn_keep_verilog).addAttribute(syn_keep_vhdl)
 }
 class PcManagerSimplePlugin(resetVector       : BigInt,
                             relaxedPcCalculation : Boolean = false,