From 64e8919e89ed647c4bea87be27bf3e5f2ce72a6b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 28 May 2019 11:28:07 +0200 Subject: [PATCH] Update README.md Add litex repo --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index b6f56ac..3fbfef0 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som - Optional interrupts and exception handling with Machine, [Supervisor] and [User] modes as defined in the [RISC-V Privileged ISA Specification v1.10](https://riscv.org/specifications/privileged-isa/). - Two implementations of shift instructions: Single cycle and shiftNumber cycles - Each stage can have optional bypass or interlock hazard logic -- Linux compatible +- Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv) - Zephyr compatible - [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV)