diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 0963de1..9099885 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -48,7 +48,7 @@ case class DataCacheConfig( cacheSize : Int,
   )
 
   def getWishboneConfig() = WishboneConfig(
-    addressWidth = 32,
+    addressWidth = 30,
     dataWidth = 32,
     selWidth = 4,
     useSTALL = false,
@@ -326,7 +326,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     }
 
 
-    bus.ADR := cmdBridge.address
+    bus.ADR := cmdBridge.address >> 2
     bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
     bus.BTE := "00"
     bus.SEL := cmdBridge.wr ? cmdBridge.mask | "1111"
diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index 2b77a5d..c1171a4 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -44,7 +44,7 @@ case class InstructionCacheConfig( cacheSize : Int,
   )
 
   def getWishboneConfig() = WishboneConfig(
-    addressWidth = 32,
+    addressWidth = 30,
     dataWidth = 32,
     selWidth = 4,
     useSTALL = false,
@@ -172,7 +172,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
     val pending = counter =/= 0
     val lastCycle = counter === counter.maxValue
 
-    bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter @@ "00"
+    bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter
     bus.CTI := lastCycle ? B"111" | B"010"
     bus.BTE := "00"
     bus.SEL := "1111"
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 7d9a0b8..99317f3 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -710,12 +710,11 @@ public:
 	virtual void preCycle(){
 	    top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32);
 		if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) {
-			assertEq(top->iBusWishbone_ADR & 3,0);
 			if(top->iBusWishbone_WE){
 
 			} else {
 		        bool error;
-			    ws->iBusAccess(top->iBusWishbone_ADR,&top->iBusWishbone_DAT_MISO,&error);
+			    ws->iBusAccess(top->iBusWishbone_ADR << 2,&top->iBusWishbone_DAT_MISO,&error);
 			    top->iBusWishbone_ERR = error;
 			}
 		}
@@ -848,13 +847,12 @@ public:
 	virtual void preCycle(){
 	    top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32);
 		if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) {
-			assertEq(top->dBusWishbone_ADR & 3,0);
 			if(top->dBusWishbone_WE){
 			    bool dummy;
-                ws->dBusAccess(top->dBusWishbone_ADR,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy);
+                ws->dBusAccess(top->dBusWishbone_ADR << 2 ,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy);
 			} else {
 			    bool error;
-			    ws->dBusAccess(top->dBusWishbone_ADR,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error);
+			    ws->dBusAccess(top->dBusWishbone_ADR << 2,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error);
                 top->dBusWishbone_ERR = error;
 			}
 		}