From 65cda9517681f0a2714a05a0cdaf87bfe97a3f68 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 17 Sep 2021 09:43:30 +0200 Subject: [PATCH] Fix wishbone bridges with datawidth > 32 --- src/main/scala/vexriscv/ip/DataCache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index ccf4803..c5e2487 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -334,7 +334,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave val cmdBridge = Stream (DataCacheMemCmd(p)) val isBurst = cmdBridge.isBurst cmdBridge.valid := cmd.valid - cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits))) + cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto addressShift) @@ U(0, addressShift bits))) cmdBridge.wr := cmd.wr cmdBridge.mask := cmd.mask cmdBridge.data := cmd.data @@ -351,7 +351,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave } - bus.ADR := cmdBridge.address >> 2 + bus.ADR := cmdBridge.address >> addressShift bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000") bus.BTE := B"00" bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)