From 662d76e3aa99e21e1c6029bd888b2931332057cf Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 3 Nov 2018 11:29:30 +0100 Subject: [PATCH] csrPlugin : avoid using ALU to get SRC1 (which was useless) --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 37f45b9..fda8474 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -282,8 +282,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)]( IS_CSR -> True, REGFILE_WRITE_VALID -> True, - ALU_BITWISE_CTRL -> AluBitwiseCtrlEnum.SRC1, - ALU_CTRL -> AluCtrlEnum.BITWISE + BYPASSABLE_MEMORY_STAGE -> True ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil) val nonImmediatActions = defaultCsrActions ++ List( @@ -786,7 +785,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val imm = IMM(input(INSTRUCTION)) - val writeSrc = input(REGFILE_WRITE_DATA) + val writeSrc = input(SRC1) val readData = B(0, 32 bits) // def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT // val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck)