From 671aa5050e97547192914ab4368dfb70e875a872 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Fri, 4 Aug 2017 14:55:54 +0200 Subject: [PATCH] Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding) Add MuraxConfig.fast --- src/main/ressource/hex/muraxDemo.elf | Bin 0 -> 27580 bytes src/main/scala/vexriscv/demo/Murax.scala | 183 ++++++++++-------- .../scala/vexriscv/demo/SynthesisBench.scala | 7 +- 3 files changed, 99 insertions(+), 91 deletions(-) create mode 100755 src/main/ressource/hex/muraxDemo.elf diff --git a/src/main/ressource/hex/muraxDemo.elf b/src/main/ressource/hex/muraxDemo.elf new file mode 100755 index 0000000000000000000000000000000000000000..ae50b215b4bd59ace808bdb0a2323c01630088fe GIT binary patch literal 27580 zcmeHwd3apamFIo+s#LON$+Bgz&04s;$csv~FD!wwRI)26EvQN$(&_IZ%VoPj8}VTs#w8H#8G$y=o@7`tF(F%72^*t~fjs419kk7<%d5 z;D$He4X!iZ3$`wLFSz>fd%>08e=oS=rT2n?H{NS8jCWrb7oE31aM;|xVxMUSv*!Mw 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HcmV?d00001 diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 6635fb5..e977a91 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -12,6 +12,8 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl} import vexriscv.plugin._ import vexriscv.{plugin, VexRiscvConfig, VexRiscv} +import scala.collection.mutable.ArrayBuffer + /** * Created by PIC32F_USER on 28/07/2017. * @@ -29,31 +31,105 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv} case class MuraxConfig(coreFrequency : HertzNumber, - onChipRamSize : BigInt, - onChipRamHexFile : String, - bypassExecute : Boolean, - bypassMemory: Boolean, - bypassWriteBack: Boolean, - bypassWriteBackBuffer : Boolean, - pipelineDBus : Boolean, - pipelineMainBus : Boolean, - pipelineApbBridge : Boolean){ + onChipRamSize : BigInt, + onChipRamHexFile : String, + pipelineDBus : Boolean, + pipelineMainBus : Boolean, + pipelineApbBridge : Boolean, + gpioWidth : Int, + uartCtrlConfig : UartCtrlMemoryMappedConfig, + cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") } object MuraxConfig{ def default = MuraxConfig( - coreFrequency = 12 MHz, - onChipRamSize = 8 kB, - onChipRamHexFile = null, - bypassExecute = false, - bypassMemory = false, - bypassWriteBack = false, - bypassWriteBackBuffer = false, - pipelineDBus = true, - pipelineMainBus = false, - pipelineApbBridge = true + coreFrequency = 12 MHz, + onChipRamSize = 8 kB, + onChipRamHexFile = null, + pipelineDBus = true, + pipelineMainBus = false, + pipelineApbBridge = true, + gpioWidth = 32, + cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel + new PcManagerSimplePlugin( + resetVector = 0x00000000l, + relaxedPcCalculation = true + ), + new IBusSimplePlugin( + interfaceKeepData = false, + catchAccessFault = false + ), + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false, + earlyInjection = false + ), + new CsrPlugin(CsrPluginConfig.smallest), + new DecoderSimplePlugin( + catchIllegalInstruction = false + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = false + ), + new LightShifterPlugin, + new HazardSimplePlugin( + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = false, + prediction = NONE + ), + new YamlPlugin("cpu0.yaml") + ), + uartCtrlConfig = UartCtrlMemoryMappedConfig( + uartCtrlConfig = UartCtrlGenerics( + dataWidthMax = 8, + clockDividerWidth = 20, + preSamplingSize = 1, + samplingSize = 3, + postSamplingSize = 1 + ), + initConfig = UartCtrlInitConfig( + baudrate = 115200, + dataLength = 7, //7 => 8 bits + parity = UartParityType.NONE, + stop = UartStopType.ONE + ), + busCanWriteClockDividerConfig = false, + busCanWriteFrameConfig = false, + txFifoDepth = 16, + rxFifoDepth = 16 + ) + ) + + def fast = { + val config = default + + //Replace HazardSimplePlugin to get datapath bypass + config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true + ) + + config + } } case class SimpleBusCmd() extends Bundle{ @@ -139,51 +215,7 @@ case class Murax(config : MuraxConfig) extends Component{ //Instanciate the CPU val cpu = new VexRiscv( config = VexRiscvConfig( - plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = true - ), - new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false - ), - new DBusSimplePlugin( - catchAddressMisaligned = false, - catchAccessFault = false, - earlyInjection = false - ), - new CsrPlugin(CsrPluginConfig.smallest), - new DecoderSimplePlugin( - catchIllegalInstruction = false - ), - new RegFilePlugin( - regFileReadyKind = plugin.SYNC, - zeroBoot = true - ), - new IntAluPlugin, - new SrcPlugin( - separatedAddSub = false, - executeInsertion = false - ), - new LightShifterPlugin, - new DebugPlugin(debugClockDomain), - new HazardSimplePlugin( - bypassExecute = bypassExecute, - bypassMemory = bypassMemory, - bypassWriteBack = bypassWriteBack, - bypassWriteBackBuffer = bypassWriteBackBuffer, - pessimisticUseSrc = false, - pessimisticWriteRegFile = false, - pessimisticAddressMatch = false - ), - new BranchPlugin( - earlyBranch = false, - catchAddressMisaligned = false, - prediction = NONE - ), - new YamlPlugin("cpu0.yaml") - ) + plugins = cpuPlugins += new DebugPlugin(debugClockDomain) ) ) @@ -379,30 +411,10 @@ case class Murax(config : MuraxConfig) extends Component{ } val gpioACtrl = Apb3Gpio( - gpioWidth = 32 + gpioWidth = gpioWidth ) io.gpioA <> gpioACtrl.io.gpio - val uartCtrlConfig = UartCtrlMemoryMappedConfig( - uartCtrlConfig = UartCtrlGenerics( - dataWidthMax = 8, - clockDividerWidth = 20, - preSamplingSize = 1, - samplingSize = 3, - postSamplingSize = 1 - ), - initConfig = UartCtrlInitConfig( - baudrate = 115200, - dataLength = 7, //7 => 8 bits - parity = UartParityType.NONE, - stop = UartStopType.ONE - ), - busCanWriteClockDividerConfig = false, - busCanWriteFrameConfig = false, - txFifoDepth = 16, - rxFifoDepth = 16 - ) - val uartCtrl = Apb3UartCtrl(uartCtrlConfig) uartCtrl.io.uart <> io.uart externalInterrupt setWhen(uartCtrl.io.interrupt) @@ -454,6 +466,7 @@ case class Murax(config : MuraxConfig) extends Component{ object Murax{ def main(args: Array[String]) { SpinalVerilog(Murax(MuraxConfig.default)) +// SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) //dhrystone config (more ram) } } diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index b1be18a..202b4a0 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -107,12 +107,7 @@ object MuraxSynthesisBench { override def getName(): String = "MuraxFast" override def getRtlPath(): String = "MuraxFast.v" SpinalVerilog({ - val murax = new Murax(MuraxConfig.default.copy( - bypassExecute = true, - bypassMemory = true, - bypassWriteBack = true, - bypassWriteBackBuffer = true - )).setDefinitionName(getRtlPath().split("\\.").head) + val murax = new Murax(MuraxConfig.fast).setDefinitionName(getRtlPath().split("\\.").head) murax.io.mainClk.setName("clk") murax })