From 67d2f72a4bd0ff7c879e944ec8c2fba1b97c599c Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 7 Mar 2021 20:43:02 +0100 Subject: [PATCH] fiber sync --- src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala index a443a40..c9e3ae9 100644 --- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala +++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala @@ -43,14 +43,14 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener } def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{ - this.debugClockDomain.merge(debugCd.outputClockDomain) + this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_JTAG) } def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{ - this.debugClockDomain.merge(debugCd.outputClockDomain) + this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_JTAG_CTRL) @@ -58,7 +58,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener } def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd{ - this.debugClockDomain.merge(debugCd.outputClockDomain) + this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_BUS) @@ -67,7 +67,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener val debugBmbAccessSource = Handle[BmbAccessCapabilities] val debugBmbAccessRequirements = Handle[BmbAccessParameter] def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd{ - this.debugClockDomain.merge(debugCd.outputClockDomain) + this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_BMB) @@ -132,6 +132,9 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener } } + + logic.soon(debugReset) + val parameterGenerator = new Generator { val iBusParameter, dBusParameter = product[BmbParameter] dependencies += config