From 6956db2b21da540d889b0ff6e7cff3cea5b5f9b9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 18 Mar 2021 11:09:26 +0100 Subject: [PATCH] fpu add schedulerM2sPipe optino --- src/main/scala/vexriscv/ip/fpu/FpuCore.scala | 2 +- src/main/scala/vexriscv/ip/fpu/Interface.scala | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala index 3c160b7..256adfa 100644 --- a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala +++ b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala @@ -267,7 +267,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{ val cmdArbiter = new Area{ val arbiter = StreamArbiterFactory.noLock.roundRobin.build(FpuCmd(p), portCount) - arbiter.io.inputs <> Vec(scheduler.map(_.output)) + arbiter.io.inputs <> Vec(scheduler.map(_.output.pipelined(m2s = p.schedulerM2sPipe))) val output = arbiter.io.output.swapPayload(RfReadInput()) output.source := arbiter.io.chosen diff --git a/src/main/scala/vexriscv/ip/fpu/Interface.scala b/src/main/scala/vexriscv/ip/fpu/Interface.scala index baf0a68..9338c35 100644 --- a/src/main/scala/vexriscv/ip/fpu/Interface.scala +++ b/src/main/scala/vexriscv/ip/fpu/Interface.scala @@ -119,6 +119,7 @@ case class FpuParameter( withDouble : Boolean, asyncRegFile : Boolean = false, mulWidthA : Int = 18, mulWidthB : Int = 18, + schedulerM2sPipe : Boolean = false, sim : Boolean = false, withAdd : Boolean = true, withMul : Boolean = true,