From 6c8e97f825848ff0a1b3544845710f57199883f2 Mon Sep 17 00:00:00 2001 From: Marcus Comstedt Date: Tue, 20 Oct 2020 18:05:31 +0200 Subject: [PATCH] Update big endian instruction encoding Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the RISC-V Instruction Set Manual, the wording was changed from requiring "natural endianness" of instruction parcels to require them to be little endian. Update the big endian instruction pipe to reflect the newer requirement. --- src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 22c3606..195b7d1 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -373,10 +373,9 @@ class IBusSimplePlugin( resetVector : BigInt, fetchRsp.rsp := rspBuffer.output.payload fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin if(bigEndian){ - // inst(15 downto 0) should contain lower addressed parcel, - // and inst(31 downto 16) the higher addressed parcel + // instructions are stored in little endian byteorder fetchRsp.rsp.inst.allowOverride - fetchRsp.rsp.inst := rspBuffer.output.payload.inst.rotateLeft(16) + fetchRsp.rsp.inst := EndiannessSwap(rspBuffer.output.payload.inst) } val join = Stream(FetchRsp())