diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
index 3663098..08faa6d 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
@@ -15,8 +15,8 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
 //
 //}
 
-//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON
 
+// make clean run DBUS=CACHED_WISHBONE IBUS=CACHED_WISHBONE MMU=no CSR=no DEBUG_PLUGIN=no
 object VexRiscvCachedWishboneForSim{
   def main(args: Array[String]) {
     val report = SpinalVerilog{
diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index bde7b6f..bee154c 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -304,7 +304,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
   def toWishbone(): Wishbone = {
     val wishboneConfig = p.getWishboneConfig()
     val bus = Wishbone(wishboneConfig)
-    val counter = Reg(UInt(log2Up(p.burstSize) bits))
+    val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
 
     val cmdBridge = Stream (DataCacheMemCmd(p))
     cmdBridge.valid := cmd.valid
@@ -333,11 +333,11 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     bus.WE  := cmdBridge.wr
     bus.DAT_MOSI := cmdBridge.data
 
-    cmdBridge.ready := bus.ACK
+    cmdBridge.ready := cmdBridge.valid && bus.ACK
     bus.CYC := cmdBridge.valid
     bus.STB := cmdBridge.valid
 
-    rsp.valid := RegNext(bus.WE && bus.ACK) init(False)
+    rsp.valid := RegNext(cmdBridge.valid && !bus.WE && bus.ACK) init(False)
     rsp.data  := RegNext(bus.DAT_MISO)
     rsp.error := False //TODO
     bus
diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index 62b9709..2b77a5d 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -168,7 +168,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
   def toWishbone(): Wishbone = {
     val wishboneConfig = p.getWishboneConfig()
     val bus = Wishbone(wishboneConfig)
-    val counter = Reg(UInt(log2Up(p.burstSize) bits))
+    val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
     val pending = counter =/= 0
     val lastCycle = counter === counter.maxValue
 
@@ -188,8 +188,8 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
       }
     }
 
-    cmd.ready := !pending
-    rsp.valid := RegNext(bus.ACK) init(False)
+    cmd.ready := cmd.valid && bus.ACK
+    rsp.valid := RegNext(bus.CYC && bus.ACK) init(False)
     rsp.data := RegNext(bus.DAT_MISO)
     rsp.error := False //TODO
     bus
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index af0fcda..f9634b9 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -686,6 +686,49 @@ public:
 };
 #endif
 
+
+#ifdef IBUS_CACHED_WISHBONE
+#include <queue>
+
+
+class IBusCachedWishbone : public SimElement{
+public:
+
+	Workspace *ws;
+	VVexRiscv* top;
+
+	IBusCachedWishbone(Workspace* ws){
+		this->ws = ws;
+		this->top = ws->top;
+	}
+
+	virtual void onReset(){
+		top->iBusWishbone_ACK = !ws->iStall;
+		top->iBusWishbone_ERR = 0;
+	}
+
+	virtual void preCycle(){
+	    top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32);
+		if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) {
+			assertEq(top->iBusWishbone_ADR & 3,0);
+			if(top->iBusWishbone_WE){
+
+			} else {
+		        bool error;
+			    ws->iBusAccess(top->iBusWishbone_ADR,&top->iBusWishbone_DAT_MISO,&error);
+			    top->iBusWishbone_ERR = error;
+			}
+		}
+	}
+
+	virtual void postCycle(){
+		if(ws->iStall)
+			top->iBusWishbone_ACK = VL_RANDOM_I(7) < 100;
+	}
+};
+#endif
+
+
 #ifdef DBUS_SIMPLE
 class DBusSimple : public SimElement{
 public:
@@ -782,8 +825,48 @@ public:
 };
 #endif
 
+#ifdef DBUS_CACHED_WISHBONE
+#include <queue>
 
 
+class DBusCachedWishbone : public SimElement{
+public:
+
+	Workspace *ws;
+	VVexRiscv* top;
+
+	DBusCachedWishbone(Workspace* ws){
+		this->ws = ws;
+		this->top = ws->top;
+	}
+
+	virtual void onReset(){
+		top->dBusWishbone_ACK = !ws->iStall;
+		top->dBusWishbone_ERR = 0;
+	}
+
+	virtual void preCycle(){
+	    top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32);
+		if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) {
+			assertEq(top->dBusWishbone_ADR & 3,0);
+			if(top->dBusWishbone_WE){
+			    bool dummy;
+                ws->dBusAccess(top->dBusWishbone_ADR,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy);
+			} else {
+			    bool error;
+			    ws->dBusAccess(top->dBusWishbone_ADR,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error);
+                top->dBusWishbone_ERR = error;
+			}
+		}
+	}
+
+	virtual void postCycle(){
+		if(ws->iStall)
+			top->dBusWishbone_ACK = VL_RANDOM_I(7) < 100;
+	}
+};
+#endif
+
 #ifdef DBUS_CACHED
 
 //#include "VVexRiscv_DataCache.h"
@@ -1216,6 +1299,9 @@ void Workspace::fillSimELements(){
 	#ifdef IBUS_CACHED_AVALON
 		simElements.push_back(new IBusCachedAvalon(this));
 	#endif
+	#ifdef IBUS_CACHED_WISHBONE
+		simElements.push_back(new IBusCachedWishbone(this));
+	#endif
 	#ifdef DBUS_SIMPLE
 		simElements.push_back(new DBusSimple(this));
 	#endif
@@ -1228,6 +1314,9 @@ void Workspace::fillSimELements(){
 	#ifdef DBUS_CACHED_AVALON
 		simElements.push_back(new DBusCachedAvalon(this));
 	#endif
+	#ifdef DBUS_CACHED_WISHBONE
+		simElements.push_back(new DBusCachedWishbone(this));
+	#endif
 	#ifdef DEBUG_PLUGIN_STD
 		simElements.push_back(new DebugPluginStd(this));
 	#endif