From 702db29edd8fa6d8f90377e660f9e4ec425f3c14 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 4 Jun 2018 20:03:08 +0200 Subject: [PATCH] Fix dynamic prediction RVC allignement --- src/main/scala/vexriscv/plugin/Fetcher.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 6c4a5c2..39c83cd 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -452,7 +452,10 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val branchContext = branchStage.input(PREDICTION_CONTEXT) val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb - historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + (if(pipeline(RVC_GEN)) + ((!branchStage.input(IS_RVC) && branchStage.input(PC)(1)) ? U(1) | U(0)) + else + U(0)) historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1)) val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue))) @@ -562,6 +565,11 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring) + + + ifGen(compressedGen)({ + // val decompressionFalure = decompressor.output. + }) } } }