From 708a8f66de664f4967d4994977e10e4e38eb35a4 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 17 Jul 2017 14:01:35 +0200 Subject: [PATCH] typo fixes --- README.md | 2 +- src/main/scala/VexRiscv/demo/GenSmallest.scala | 3 ++- src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 7542acf..f179805 100644 --- a/README.md +++ b/README.md @@ -59,7 +59,7 @@ VexRiscv full (RV32IM, 1.14 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debu Cyclone IV -> 116 Mhz 2727 LUT 1759 FF Cyclone II -> 105 Mhz 2771 LUT 1758 FF -VexRiscv full with MMU (RV32IM, 1.16 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, static branch, MMU) -> +VexRiscv full with MMU (RV32IM, 1.16 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) -> Artix 7 -> 210 Mhz 2104 LUT 2017 FF Cyclone V -> 115 Mhz 1503 ALMs Cyclone IV -> 100 Mhz 3145 LUT 2278 FF diff --git a/src/main/scala/VexRiscv/demo/GenSmallest.scala b/src/main/scala/VexRiscv/demo/GenSmallest.scala index cba57d1..c0369e7 100644 --- a/src/main/scala/VexRiscv/demo/GenSmallest.scala +++ b/src/main/scala/VexRiscv/demo/GenSmallest.scala @@ -30,7 +30,8 @@ object GenSmallest extends App{ ), new IntAluPlugin, new SrcPlugin( - separatedAddSub = false + separatedAddSub = false, + executeInsertion = false ), new LightShifterPlugin, new HazardSimplePlugin( diff --git a/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala b/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala index 1039016..018d0e6 100644 --- a/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala @@ -29,7 +29,8 @@ object GenSmallestNoCsr extends App{ ), new IntAluPlugin, new SrcPlugin( - separatedAddSub = false + separatedAddSub = false, + executeInsertion = false ), new LightShifterPlugin, new HazardSimplePlugin(