From 711eed1e77230840233a8cbc502e83ee47a41990 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 11 Oct 2019 00:23:29 +0200
Subject: [PATCH] MulPlugin add withInputBuffer feature and now use RSx instead
 of SRCx

---
 .../scala/vexriscv/plugin/MulPlugin.scala     | 29 +++++++++++++++----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/MulPlugin.scala b/src/main/scala/vexriscv/plugin/MulPlugin.scala
index ab4d828..96db3e9 100644
--- a/src/main/scala/vexriscv/plugin/MulPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/MulPlugin.scala
@@ -3,7 +3,8 @@ import vexriscv._
 import vexriscv.VexRiscv
 import spinal.core._
 
-class MulPlugin extends Plugin[VexRiscv]{
+//Input buffer generaly avoid the FPGA synthesis to duplicate reg inside the DSP cell, which could stress timings quite much.
+class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{
   object MUL_LL extends Stageable(UInt(32 bits))
   object MUL_LH extends Stageable(SInt(34 bits))
   object MUL_HL extends Stageable(SInt(34 bits))
@@ -19,8 +20,8 @@ class MulPlugin extends Plugin[VexRiscv]{
 
 
     val actions = List[(Stageable[_ <: BaseType],Any)](
-      SRC1_CTRL                -> Src1CtrlEnum.RS,
-      SRC2_CTRL                -> Src2CtrlEnum.RS,
+//      SRC1_CTRL                -> Src1CtrlEnum.RS,
+//      SRC2_CTRL                -> Src2CtrlEnum.RS,
       REGFILE_WRITE_VALID      -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE  -> False,
@@ -48,8 +49,26 @@ class MulPlugin extends Plugin[VexRiscv]{
       val aSigned,bSigned = Bool
       val a,b = Bits(32 bit)
 
-      a := input(SRC1)
-      b := input(SRC2)
+//      a := input(SRC1)
+//      b := input(SRC2)
+
+      val withInputBuffer = inputBuffer generate new Area{
+        val rs1 = RegNext(input(RS1))
+        val rs2 = RegNext(input(RS2))
+        a := rs1
+        b := rs2
+
+        val delay = RegNext(arbitration.isStuck)
+        when(arbitration.isValid && input(IS_MUL) && !delay){
+          arbitration.haltItself := True
+        }
+      }
+
+      val noInputBuffer = (!inputBuffer) generate new Area{
+        a := input(RS1)
+        b := input(RS2)
+      }
+
       switch(input(INSTRUCTION)(13 downto 12)) {
         is(B"01") {
           aSigned := True