From 73f88e47cb83d71c2bc29669054d165652eb8fcc Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 3 Jun 2020 16:29:21 +0200 Subject: [PATCH] Fix BmbToLitexDram coherency --- src/main/scala/vexriscv/demo/smp/Misc.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/smp/Misc.scala b/src/main/scala/vexriscv/demo/smp/Misc.scala index a7965a4..b192a9c 100644 --- a/src/main/scala/vexriscv/demo/smp/Misc.scala +++ b/src/main/scala/vexriscv/demo/smp/Misc.scala @@ -205,10 +205,17 @@ case class BmbToLiteDram(bmbParameter : BmbParameter, val rspContext = cmdContext.queue(rdataFifoSize) val rdataFifo = io.output.rdata.queueLowLatency(rdataFifoSize, latency = 1) + val writeTocken = CounterUpDown( + stateCount = rdataFifoSize*2, + incWhen = io.output.wdata.fire, + decWhen = rspContext.fire && rspContext.isWrite + ) + val canRspWrite = writeTocken =/= 0 + val canRspRead = CombInit(rdataFifo.valid) rdataFifo.ready := unburstified.rsp.fire && !rspContext.isWrite rspContext.ready := unburstified.rsp.fire - unburstified.rsp.valid := rspContext.valid && (rspContext.isWrite || rdataFifo.valid) + unburstified.rsp.valid := rspContext.valid && (rspContext.isWrite ? canRspWrite | canRspRead) unburstified.rsp.setSuccess() unburstified.rsp.last := True unburstified.rsp.source := rspContext.source