From 74f2a4194a8d28b3626165493ad2ddab0f86f8d6 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Fri, 20 Apr 2018 17:56:21 +0200
Subject: [PATCH] Add ExternalInterruptArrayPlugin

---
 .../plugin/ExternalInterruptArrayPlugin.scala | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala

diff --git a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
new file mode 100644
index 0000000..b205f0f
--- /dev/null
+++ b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
@@ -0,0 +1,21 @@
+package vexriscv.plugin
+
+import spinal.core._
+import vexriscv.VexRiscv
+
+class ExternalInterruptArrayPlugin(arrayWidth : Int = 32) extends Plugin[VexRiscv]{
+  var externalInterruptArray : Bits = null
+
+  override def setup(pipeline: VexRiscv): Unit = {
+    externalInterruptArray = in(Bits(arrayWidth bits)).setName("externalInterruptArray")
+  }
+
+  override def build(pipeline: VexRiscv): Unit = {
+    val csr = pipeline.service(classOf[CsrPlugin])
+    val mask = Reg(Bits(arrayWidth bits)) init(0)
+    val pendings = mask & RegNext(externalInterruptArray)
+    csr.externalInterrupt.asDirectionLess() := pendings.orR
+    csr.rw(0x330, mask)
+    csr.r(0x360, pendings)
+  }
+}