From 760a0fced5a574a02a3557fb08ce178b4c9b20b1 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 23 May 2023 18:18:53 +0200 Subject: [PATCH] Update SpinalHDL --- src/main/scala/vexriscv/ip/DataCache.scala | 3 ++- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index 848c347..5ed44f6 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -168,8 +168,9 @@ case class FenceFlags() extends Bundle { def forceAll(): Unit ={ List(SW,SR,SO,SI,PW,PR,PO,PI).foreach(_ := True) } - def clearAll(): Unit ={ + def clearFlags(): this.type ={ List(SW,SR,SO,SI,PW,PR,PO,PI).foreach(_ := False) + this } } diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index bcdad63..593eb91 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -501,7 +501,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, } when(!input(MEMORY_FENCE) || !arbitration.isFiring){ - cache.io.cpu.writeBack.fence.clearAll() + cache.io.cpu.writeBack.fence.clearFlags() } when(arbitration.isValid && (input(MEMORY_FENCE) || aquire)){