diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index 5c1a34b..de29409 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -40,6 +40,7 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
     val externalSupervisorInterrupts = in Bits(p.cpuConfigs.size bits)
     val jtag = slave(Jtag())
     val debugReset = out Bool()
+    val time = in UInt(64 bits)
   }
 
   val cpus = for((cpuConfig, cpuId) <- p.cpuConfigs.zipWithIndex) yield new Area{
@@ -61,6 +62,7 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
         plugin.externalInterrupt := io.externalInterrupts(cpuId)
         plugin.timerInterrupt := io.timerInterrupts(cpuId)
         if (plugin.config.supervisorGen) plugin.externalInterruptS := io.externalSupervisorInterrupts(cpuId)
+        if (plugin.utime != null) plugin.utime := io.time
       }
       case plugin: DebugPlugin => debugClockDomain{
         io.debugReset := RegNext(plugin.io.resetOut)
@@ -517,6 +519,9 @@ object VexRiscvSmpClusterOpenSbi extends App{
       var lastAddress = 0l
     })
     dut.clockDomain.onSamplings{
+      dut.io.time #= simTime()/10
+
+
       for(i <- 0 until cpuCount; iMem = dut.io.iMems(i); ctx = iMemCtx(i)){
 //        if(iMem.cmd.valid.toBoolean && iMem.cmd.ready.toBoolean){
 //          val length = iMem.cmd.length.toInt + 1
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index ea5cd39..9466cfe 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -57,6 +57,7 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
   cluster.io.debugReset <> io.debugReset
   cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
   cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
+  cluster.io.time := clint.time
 
   val dBusDecoder = BmbDecoderOutOfOrder(
     p            = cluster.io.dMem.p,
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala
index ceb5a36..0f2af9b 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala
@@ -58,6 +58,7 @@ case class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter,
   cluster.io.debugReset <> io.debugReset
   cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
   cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
+  cluster.io.time := clint.time
 
   val dBusDecoder = BmbDecoderOutOfOrder(
     p            = cluster.io.dMem.p,
@@ -253,6 +254,7 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
         (dut.io.peripheral.ADR.toLong << 2) match {
           case 0xF0000000l => print(dut.io.peripheral.DAT_MOSI.toLong.toChar)
           case 0xF0000004l => dut.io.peripheral.DAT_MISO #= (if (System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
+          case _ =>
           //            case 0xF0000004l => {
           //              val c = if(stdin.nonEmpty) {
           //                stdin.dequeue().toInt & 0xFF