From 771eaf431e75d535ae3d14c4ee3541fbcd092d70 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 24 May 2022 12:15:57 +0200 Subject: [PATCH] Better cache invalidation doc --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a02c52b..760c63c 100644 --- a/README.md +++ b/README.md @@ -1038,7 +1038,7 @@ There is at least one cycle latency between a cmd and the corresponding rsp. The Multi way cache implementation with writh-through and allocate on read strategy. (Documentation is WIP) -You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range of one line via the instruction 0x500F | RS1 << 15 where RS1 should not be X0. +You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range (single line size) via the instruction 0x500F | RS1 << 15 where RS1 should not be X0 and point to one byte of the desired address to invalidate. #### MulPlugin