From a34079884093901842f20917b9a41638213f3eb9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 18 Dec 2021 09:11:08 +0100 Subject: [PATCH 01/11] Update build.properties --- project/build.properties | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/build.properties b/project/build.properties index 72f9028..0b2e09c 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.2.7 +sbt.version=1.4.7 From 34e5cafb75142842dd8db7ed64d7d161ddbfd4ef Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 20 Dec 2021 09:38:02 +0100 Subject: [PATCH 02/11] Enable scala 2.13 compatibility --- .../scala/spinal/lib/eda/icestorm/IcestormFlow.scala | 2 ++ src/main/scala/vexriscv/VexRiscv.scala | 9 +++++---- src/main/scala/vexriscv/demo/Briey.scala | 2 +- src/main/scala/vexriscv/demo/Murax.scala | 5 +++-- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala b/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala index b6ab7b5..6ef8d08 100644 --- a/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala +++ b/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala @@ -13,6 +13,8 @@ import spinal.lib.eda.bench.Report import scala.sys.process._ +import scala.collection.Seq + object IcestormFlow { def doCmd(cmd : Seq[String], path : String): String ={ println(cmd) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 2bc647d..d3feda3 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -4,6 +4,7 @@ import vexriscv.plugin._ import spinal.core._ import scala.collection.mutable.ArrayBuffer +import scala.collection.Seq object VexRiscvConfig{ def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = { @@ -135,10 +136,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ plugins ++= config.plugins //regression usage - val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)) keep() addAttribute (Verilator.public) - val lastStagePc = CombInit(stages.last.input(config.PC)) keep() addAttribute (Verilator.public) - val lastStageIsValid = CombInit(stages.last.arbitration.isValid) keep() addAttribute (Verilator.public) - val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring) keep() addAttribute (Verilator.public) + val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)).keep().addAttribute (Verilator.public) + val lastStagePc = CombInit(stages.last.input(config.PC)).keep().addAttribute(Verilator.public) + val lastStageIsValid = CombInit(stages.last.arbitration.isValid).keep().addAttribute(Verilator.public) + val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring).keep().addAttribute(Verilator.public) //Verilator perf decode.arbitration.removeIt.noBackendCombMerge diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala index 701af7b..32e6d62 100644 --- a/src/main/scala/vexriscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -24,7 +24,7 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal} import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, JtagBridge, SystemDebugger, SystemDebuggerConfig} import scala.collection.mutable.ArrayBuffer - +import scala.collection.Seq case class BrieyConfig(axiFrequency : HertzNumber, onChipRamSize : BigInt, diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 05c8e00..7c679a1 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -16,6 +16,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} import spinal.lib.com.spi.ddr._ import spinal.lib.bus.simple._ import scala.collection.mutable.ArrayBuffer +import scala.collection.Seq /** * Created by PIC32F_USER on 28/07/2017. @@ -313,13 +314,13 @@ case class Murax(config : MuraxConfig) extends Component{ //******** Memory mappings ********* val apbDecoder = Apb3Decoder( master = apbBridge.io.apb, - slaves = apbMapping + slaves = apbMapping.toSeq ) val mainBusDecoder = new Area { val logic = new MuraxPipelinedMemoryBusDecoder( master = mainBusArbiter.io.masterBus, - specification = mainBusMapping, + specification = mainBusMapping.toSeq, pipelineMaster = pipelineMainBus ) } From f46ad43f393cd345ca0f81ed716eaddcb7d76e4b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jan 2022 13:39:41 +0100 Subject: [PATCH 03/11] DataCache.withInternalLrSc reserved clearing fix --- src/main/scala/vexriscv/ip/DataCache.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index c5e2487..43bb919 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -864,8 +864,8 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam val lrSc = withInternalLrSc generate new Area{ val reserved = RegInit(False) - when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.isLrsc){ - reserved := !request.wr + when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){ + reserved := False } } @@ -1167,4 +1167,4 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam s1.invalidations := RegNextWhen((input.valid && input.enable && input.address(lineRange) === s0.input.address(lineRange)) ? wayHits | 0, s0.input.ready) } } -} \ No newline at end of file +} From da53de360f2ee9ca64375c2773b9cc2cb1fe8b28 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jan 2022 14:21:20 +0100 Subject: [PATCH 04/11] Fix lrsc from last commit --- src/main/scala/vexriscv/ip/DataCache.scala | 5 +++-- src/test/cpp/regression/main.cpp | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index 43bb919..02d3e9a 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -864,8 +864,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam val lrSc = withInternalLrSc generate new Area{ val reserved = RegInit(False) - when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){ - reserved := False + when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck){ + reserved setWhen(request.isLrsc) + reserved clearWhen(request.wr) } } diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 82cc4d3..b5df2ef 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -898,6 +898,7 @@ public: status.fs = 3; pcWrite(pc + 4); } + lrscReserved = false; } break; #endif case 0x37:rfWrite(rd32, i & 0xFFFFF000);pcWrite(pc + 4);break; // LUI @@ -949,6 +950,7 @@ public: dWrite(pAddr, size, (uint8_t*)&i32_rs2); pcWrite(pc + 4); } + lrscReserved = false; }break; case 0x13: //ALUi switch ((i >> 12) & 0x7) { @@ -1107,9 +1109,7 @@ public: int32_t src = i32_rs2; int32_t readValue; - #ifdef DBUS_EXCLUSIVE lrscReserved = false; - #endif uint32_t pAddr; if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; } From 6e77f320871e04663ea4c553a8e24cc55a925239 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jan 2022 16:08:38 +0100 Subject: [PATCH 05/11] sim golden model lrsc reservation sync --- src/test/cpp/regression/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index b5df2ef..1b316e9 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -897,8 +897,8 @@ public: dWrite(pAddr, size, (uint8_t*) &rsp.value); status.fs = 3; pcWrite(pc + 4); + lrscReserved = false; } - lrscReserved = false; } break; #endif case 0x37:rfWrite(rd32, i & 0xFFFFF000);pcWrite(pc + 4);break; // LUI @@ -949,8 +949,8 @@ public: if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } dWrite(pAddr, size, (uint8_t*)&i32_rs2); pcWrite(pc + 4); + lrscReserved = false; } - lrscReserved = false; }break; case 0x13: //ALUi switch ((i >> 12) & 0x7) { From b8e904e43f8284768c8b663f76a3385390330b7f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jan 2022 19:55:28 +0100 Subject: [PATCH 06/11] syncronize golden model with dut for lrsc reservation --- src/main/scala/vexriscv/ip/DataCache.scala | 5 +++-- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 1 + src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 5 +++-- src/test/cpp/regression/main.cpp | 7 +++++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index 02d3e9a..b3cf4dc 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -175,6 +175,7 @@ case class FenceFlags() extends Bundle { case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMasterSlave{ val isValid = Bool() val isStuck = Bool() + val isFiring = Bool() val isUser = Bool() val haltIt = Bool() val isWrite = Bool() @@ -187,7 +188,7 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste val exclusiveOk = Bool() override def asMaster(): Unit = { - out(isValid,isStuck,isUser, address, fence, storeData) + out(isValid,isStuck,isUser, address, fence, storeData, isFiring) in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite, keepMemRspData, exclusiveOk) } } @@ -864,7 +865,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam val lrSc = withInternalLrSc generate new Area{ val reserved = RegInit(False) - when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck){ + when(io.cpu.writeBack.isValid && io.cpu.writeBack.isFiring){ reserved setWhen(request.isLrsc) reserved clearWhen(request.wr) } diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 99786e7..3fb6498 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -395,6 +395,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, import managementStage._ cache.io.cpu.writeBack.isValid := arbitration.isValid && input(MEMORY_ENABLE) cache.io.cpu.writeBack.isStuck := arbitration.isStuck + cache.io.cpu.writeBack.isFiring := arbitration.isFiring cache.io.cpu.writeBack.isUser := (if(privilegeService != null) privilegeService.isUser() else False) cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA)) cache.io.cpu.writeBack.storeData.subdivideIn(32 bits).foreach(_ := input(MEMORY_STORE_DATA_RF)) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index ac22dc4..d96d312 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -462,8 +462,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, val atomic = withLrSc generate new Area{ val reserved = RegInit(False) insert(ATOMIC_HIT) := reserved - when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){ - reserved := !input(MEMORY_STORE) + when(arbitration.isFiring && input(MEMORY_ENABLE) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){ + reserved setWhen(input(MEMORY_ATOMIC)) + reserved clearWhen(input(MEMORY_STORE)) } when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){ skipCmd := True diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 1b316e9..0178001 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -949,7 +949,7 @@ public: if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } dWrite(pAddr, size, (uint8_t*)&i32_rs2); pcWrite(pc + 4); - lrscReserved = false; + lrscReserved = false; } }break; case 0x13: //ALUi @@ -1111,6 +1111,7 @@ public: lrscReserved = false; + uint32_t pAddr; if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; } if(dRead(pAddr, 4, (uint8_t*)&readValue)){ @@ -1178,6 +1179,7 @@ public: if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } dWrite(pAddr, 4, (uint8_t*)&i16_rf2); pcWrite(pc + 2); + lrscReserved = false; } }break; case 8: rfWrite(rd32, regs[rd32] + i16_imm); pcWrite(pc + 2); break; @@ -1243,6 +1245,7 @@ public: } else { if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } dWrite(pAddr, 4, (uint8_t*)®s[iBits(2,5)]); pcWrite(pc + 2); + lrscReserved = false; } }break; } @@ -2610,7 +2613,6 @@ public: bool hit = reservationValid && reservationAddress == top->dBus_cmd_payload_address; rsp.exclusive = hit; cancel = !hit; - reservationValid = false; } if(!cancel) { for(int idx = 0;idx < 1;idx++){ @@ -2621,6 +2623,7 @@ public: } } + reservationValid = false; rsp.last = true; rsp.error = error; rsps.push(rsp); From 9c34a1fd2e2bf4bb313bed8169bc4bcb3bb1b6fc Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 14 Jan 2022 09:59:22 +0100 Subject: [PATCH 07/11] updated related to JtagInstructionWrapper.ignoreWidth --- src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 2 +- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 3 ++- .../scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala | 6 ++++-- src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 4 ++-- src/main/scala/vexriscv/plugin/DebugPlugin.scala | 8 ++++---- 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala index 723ea7d..3ff3334 100644 --- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala +++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala @@ -113,7 +113,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener withDebug.get match { case DEBUG_JTAG => jtag <> plugin.io.bus.fromJtag() - case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain) + case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain, 0) case DEBUG_BUS => debugBus <> plugin.io.bus case DEBUG_BMB => debugBmb >> plugin.io.bus.fromBmb() } diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index 54941d4..743d2c2 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -26,6 +26,7 @@ import spinal.lib.generator._ import vexriscv.ip.fpu.FpuParameter case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], + jtagHeaderIgnoreWidth : Int, withExclusiveAndInvalidation : Boolean, forcePeripheralWidth : Boolean = true, outOfOrderDecoder : Boolean = true, @@ -51,7 +52,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with implicit val interconnect = BmbInterconnectGenerator() - val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator() + val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator(p.jtagHeaderIgnoreWidth) debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false)) val debugPort = Handle(debugBridge.logic.jtagBridge.io.ctrl.toIo) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala index 7a20b30..4cd4917 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala @@ -175,7 +175,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App { withExclusiveAndInvalidation = coherency, forcePeripheralWidth = !wishboneMemory, outOfOrderDecoder = outOfOrderDecoder, - fpu = fpu + fpu = fpu, + jtagHeaderIgnoreWidth = 0 ), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth), liteDramMapping = SizeMapping(0x40000000l, 0x40000000l), @@ -250,7 +251,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{ resetVector = 0x80000000l ) }, - withExclusiveAndInvalidation = true + withExclusiveAndInvalidation = true, + jtagHeaderIgnoreWidth = 0 ), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128), liteDramMapping = SizeMapping(0x80000000l, 0x70000000l), diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index d96d312..094de17 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -567,8 +567,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, } } - if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage) - assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend") +// if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage) +// assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend") //formal insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA) diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index cc7ca33..87d4f56 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -137,13 +137,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{ jtagBridge.io.jtag } - def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={ + def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain, jtagHeaderIgnoreWidth : Int): JtagTapInstructionCtrl ={ val jtagConfig = SystemDebuggerConfig( memAddressWidth = 32, memDataWidth = 32, remoteCmdWidth = 1 ) - val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain) + val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth) val debugger = new SystemDebugger(jtagConfig) debugger.io.remote <> jtagBridge.io.remote debugger.io.mem <> this.from(jtagConfig) @@ -151,13 +151,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{ jtagBridge.io.ctrl } - def fromBscane2(usedId : Int): Unit ={ + def fromBscane2(usedId : Int, jtagHeaderIgnoreWidth : Int): Unit ={ val jtagConfig = SystemDebuggerConfig() val bscane2 = BSCANE2(usedId) val jtagClockDomain = ClockDomain(bscane2.TCK) - val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain) + val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth) jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl() val debugger = new SystemDebugger(jtagConfig) From 8b2f107d46200793202679ec10be412bd15ca47a Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 4 Feb 2022 15:10:57 +0100 Subject: [PATCH 08/11] verilator++ --- README.md | 2 +- src/test/cpp/regression/main.cpp | 124 ++++++++++++++++--------------- 2 files changed, 64 insertions(+), 62 deletions(-) diff --git a/README.md b/README.md index 8f2eb81..1a8864b 100644 --- a/README.md +++ b/README.md @@ -182,7 +182,7 @@ unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator git pull # Make sure we're up-to-date -git checkout v4.040 +git checkout v4.216 autoconf # Create ./configure script ./configure make diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 0178001..3981b87 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -20,6 +20,8 @@ #include #include "encoding.h" +#define VL_RANDOM_I_WIDTH(w) (VL_RANDOM_I() & (1l << w)-1l) + using namespace std; struct timespec timer_get(){ @@ -1440,7 +1442,7 @@ public: } Workspace(string name){ vcdName = name; - //seed = VL_RANDOM_I(32)^VL_RANDOM_I(32)^0x1093472; + //seed = VL_RANDOM_I_WIDTH(32)^VL_RANDOM_I_WIDTH(32)^0x1093472; //srand48(seed); // setIStall(false); // setDStall(false); @@ -1853,9 +1855,9 @@ public: for(SimElement* simElement : simElements) simElement->postCycle(); #ifdef RVF - top->fpuCmdHalt = VL_RANDOM_I(1); - top->fpuCommitHalt = VL_RANDOM_I(1); - top->fpuRspHalt = VL_RANDOM_I(1); + top->fpuCmdHalt = VL_RANDOM_I_WIDTH(1); + top->fpuCommitHalt = VL_RANDOM_I_WIDTH(1); + top->fpuRspHalt = VL_RANDOM_I_WIDTH(1); #endif @@ -2052,7 +2054,7 @@ public: //TODO doesn't catch when instruction removed ? virtual void postCycle(){ top->iBus_rsp_valid = 0; - if(rPtr != wPtr && (!ws->iStall || VL_RANDOM_I(7) < 100)){ + if(rPtr != wPtr && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){ uint32_t inst_next; bool error_next; ws->iBusAccess(pendings[rPtr], &inst_next,&error_next); @@ -2061,10 +2063,10 @@ public: top->iBus_rsp_valid = 1; top->iBus_rsp_payload_error = error_next; } else { - top->iBus_rsp_payload_inst = VL_RANDOM_I(32); - top->iBus_rsp_payload_error = VL_RANDOM_I(1); + top->iBus_rsp_payload_inst = VL_RANDOM_I_WIDTH(32); + top->iBus_rsp_payload_error = VL_RANDOM_I_WIDTH(1); } - if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100; + if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I_WIDTH(7) < 100; } }; #endif @@ -2139,18 +2141,18 @@ public: } //TODO doesn't catch when instruction removed ? virtual void postCycle(){ - if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){ + if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){ IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop(); top->iBusAvalon_readDataValid = 1; top->iBusAvalon_readData = rsp.data; top->iBusAvalon_response = rsp.error ? 3 : 0; } else { top->iBusAvalon_readDataValid = 0; - top->iBusAvalon_readData = VL_RANDOM_I(32); - top->iBusAvalon_response = VL_RANDOM_I(2); + top->iBusAvalon_readData = VL_RANDOM_I_WIDTH(32); + top->iBusAvalon_response = VL_RANDOM_I_WIDTH(2); } if(ws->iStall) - top->iBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100; + top->iBusAvalon_waitRequestn = VL_RANDOM_I_WIDTH(7) < 100; } }; #endif @@ -2187,15 +2189,15 @@ public: virtual void postCycle(){ if(ws->iStall) - top->iBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100); + top->iBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100); if(pending && top->iBusAhbLite3_HREADY){ top->iBusAhbLite3_HRDATA = iBusAhbLite3_HRDATA; top->iBusAhbLite3_HRESP = iBusAhbLite3_HRESP; pending = false; } else { - top->iBusAhbLite3_HRDATA = VL_RANDOM_I(32); - top->iBusAhbLite3_HRESP = VL_RANDOM_I(1); + top->iBusAhbLite3_HRDATA = VL_RANDOM_I_WIDTH(32); + top->iBusAhbLite3_HRESP = VL_RANDOM_I_WIDTH(1); } } }; @@ -2233,7 +2235,7 @@ public: virtual void postCycle(){ bool error; top->iBus_rsp_valid = 0; - if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){ + if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){ #ifdef IBUS_TC if((address & 0x70000000) == 0){ printf("IBUS_CACHED access out of range\n"); @@ -2251,7 +2253,7 @@ public: address = address + IBUS_DATA_WIDTH/8; top->iBus_rsp_valid = 1; } - if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100 && pendingCount == 0; + if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I_WIDTH(7) < 100 && pendingCount == 0; } }; #endif @@ -2266,7 +2268,7 @@ struct IBusCachedAvalonTask{ class IBusCachedAvalon : public SimElement{ public: - uint32_t inst_next = VL_RANDOM_I(32); + uint32_t inst_next = VL_RANDOM_I_WIDTH(32); bool error_next = false; queue tasks; @@ -2296,7 +2298,7 @@ public: virtual void postCycle(){ bool error; top->iBusAvalon_readDataValid = 0; - if(!tasks.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){ + if(!tasks.empty() && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){ uint32_t &address = tasks.front().address; uint32_t &pendingCount = tasks.front().pendingCount; bool error; @@ -2309,7 +2311,7 @@ public: tasks.pop(); } if(ws->iStall) - top->iBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100; + top->iBusAvalon_waitRequestn = VL_RANDOM_I_WIDTH(7) < 100; } }; #endif @@ -2341,9 +2343,9 @@ public: virtual void postCycle(){ if(ws->iStall) - top->iBusWishbone_ACK = VL_RANDOM_I(7) < 100; + top->iBusWishbone_ACK = VL_RANDOM_I_WIDTH(7) < 100; - top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32); + top->iBusWishbone_DAT_MISO = VL_RANDOM_I_WIDTH(32); if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) { if(top->iBusWishbone_WE){ @@ -2361,7 +2363,7 @@ public: #ifdef DBUS_SIMPLE class DBusSimple : public SimElement{ public: - uint32_t data_next = VL_RANDOM_I(32); + uint32_t data_next = VL_RANDOM_I_WIDTH(32); bool error_next = false; bool pending = false; @@ -2387,16 +2389,16 @@ public: virtual void postCycle(){ top->dBus_rsp_ready = 0; - if(pending && (!ws->dStall || VL_RANDOM_I(7) < 100)){ + if(pending && (!ws->dStall || VL_RANDOM_I_WIDTH(7) < 100)){ pending = false; top->dBus_rsp_ready = 1; top->dBus_rsp_data = data_next; top->dBus_rsp_error = error_next; } else{ - top->dBus_rsp_data = VL_RANDOM_I(32); + top->dBus_rsp_data = VL_RANDOM_I_WIDTH(32); } - if(ws->dStall) top->dBus_cmd_ready = VL_RANDOM_I(7) < 100 && !pending; + if(ws->dStall) top->dBus_cmd_ready = VL_RANDOM_I_WIDTH(7) < 100 && !pending; } }; #endif @@ -2438,18 +2440,18 @@ public: } //TODO doesn't catch when instruction removed ? virtual void postCycle(){ - if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){ + if(!rsps.empty() && (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100)){ DBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop(); top->dBusAvalon_readDataValid = 1; top->dBusAvalon_readData = rsp.data; top->dBusAvalon_response = rsp.error ? 3 : 0; } else { top->dBusAvalon_readDataValid = 0; - top->dBusAvalon_readData = VL_RANDOM_I(32); - top->dBusAvalon_response = VL_RANDOM_I(2); + top->dBusAvalon_readData = VL_RANDOM_I_WIDTH(32); + top->dBusAvalon_response = VL_RANDOM_I_WIDTH(2); } if(ws->iStall) - top->dBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100; + top->dBusAvalon_waitRequestn = VL_RANDOM_I_WIDTH(7) < 100; } }; #endif @@ -2492,10 +2494,10 @@ public: virtual void postCycle(){ if(ws->iStall) - top->dBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100); + top->dBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I_WIDTH(7) < 100); - top->dBusAhbLite3_HRDATA = VL_RANDOM_I(32); - top->dBusAhbLite3_HRESP = VL_RANDOM_I(1); + top->dBusAhbLite3_HRDATA = VL_RANDOM_I_WIDTH(32); + top->dBusAhbLite3_HRESP = VL_RANDOM_I_WIDTH(1); if(top->dBusAhbLite3_HREADY && dBusAhbLite3_HTRANS == 2 && !dBusAhbLite3_HWRITE){ @@ -2534,8 +2536,8 @@ public: virtual void postCycle(){ if(ws->iStall) - top->dBusWishbone_ACK = VL_RANDOM_I(7) < 100; - top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32); + top->dBusWishbone_ACK = VL_RANDOM_I_WIDTH(7) < 100; + top->dBusWishbone_DAT_MISO = VL_RANDOM_I_WIDTH(32); if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) { if(top->dBusWishbone_WE){ bool dummy; @@ -2638,7 +2640,7 @@ public: ws->dBusAccess(top->dBus_cmd_payload_address,0,1 << top->dBus_cmd_payload_size,buffer, &error); for(int beat = 0;beat <= beatCount;beat++){ for(int i = 0;i < DBUS_LOAD_DATA_WIDTH/8;i++){ - rsp.data[i] = (address >= startAt && address < endAt) ? buffer[address-top->dBus_cmd_payload_address] : VL_RANDOM_I(8); + rsp.data[i] = (address >= startAt && address < endAt) ? buffer[address-top->dBus_cmd_payload_address] : VL_RANDOM_I_WIDTH(8); address += 1; } rsp.last = beat == beatCount; @@ -2655,8 +2657,8 @@ public: #ifdef DBUS_INVALIDATE if(ws->allowInvalidate){ - if(VL_RANDOM_I(7) < 10){ - invalidationHint.push(top->dBus_cmd_payload_address + VL_RANDOM_I(5)); + if(VL_RANDOM_I_WIDTH(7) < 10){ + invalidationHint.push(top->dBus_cmd_payload_address + VL_RANDOM_I_WIDTH(5)); } } #endif @@ -2671,7 +2673,7 @@ public: virtual void postCycle(){ - if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){ + if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I_WIDTH(7) < 100)){ DBusCachedTask rsp = rsps.front(); rsps.pop(); top->dBus_rsp_valid = 1; @@ -2686,33 +2688,33 @@ public: } else{ top->dBus_rsp_valid = 0; for(int idx = 0;idx < DBUS_LOAD_DATA_WIDTH/32;idx++){ - ((uint32_t*)&top->dBus_rsp_payload_data)[idx] = VL_RANDOM_I(32); + ((uint32_t*)&top->dBus_rsp_payload_data)[idx] = VL_RANDOM_I_WIDTH(32); } - top->dBus_rsp_payload_error = VL_RANDOM_I(1); - top->dBus_rsp_payload_last = VL_RANDOM_I(1); + top->dBus_rsp_payload_error = VL_RANDOM_I_WIDTH(1); + top->dBus_rsp_payload_last = VL_RANDOM_I_WIDTH(1); #ifdef DBUS_EXCLUSIVE - top->dBus_rsp_payload_exclusive = VL_RANDOM_I(1); + top->dBus_rsp_payload_exclusive = VL_RANDOM_I_WIDTH(1); #endif } - top->dBus_cmd_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1); + top->dBus_cmd_ready = (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 100 : 1); #ifdef DBUS_INVALIDATE if(ws->allowInvalidate){ if(top->dBus_inv_ready) top->dBus_inv_valid = 0; - if(top->dBus_inv_valid == 0 && VL_RANDOM_I(7) < 5){ + if(top->dBus_inv_valid == 0 && VL_RANDOM_I_WIDTH(7) < 5){ top->dBus_inv_valid = 1; - top->dBus_inv_payload_fragment_enable = VL_RANDOM_I(7) < 100; + top->dBus_inv_payload_fragment_enable = VL_RANDOM_I_WIDTH(7) < 100; if(!invalidationHint.empty()){ top->dBus_inv_payload_fragment_address = invalidationHint.front(); invalidationHint.pop(); } else { - top->dBus_inv_payload_fragment_address = VL_RANDOM_I(32); + top->dBus_inv_payload_fragment_address = VL_RANDOM_I_WIDTH(32); } } } - top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1); + top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 100 : 1); if(top->dBus_sync_ready) top->dBus_sync_valid = 0; - if(top->dBus_sync_valid == 0 && pendingSync != 0 && (ws->dStall ? VL_RANDOM_I(7) < 80 : 1) ){ + if(top->dBus_sync_valid == 0 && pendingSync != 0 && (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 80 : 1) ){ top->dBus_sync_valid = 1; } #endif @@ -2767,7 +2769,7 @@ public: } virtual void postCycle(){ - if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){ + if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I_WIDTH(7) < 100)){ DBusCachedAvalonTask rsp = rsps.front(); rsps.pop(); top->dBusAvalon_response = rsp.error ? 3 : 0; @@ -2775,11 +2777,11 @@ public: top->dBusAvalon_readDataValid = 1; } else{ top->dBusAvalon_readDataValid = 0; - top->dBusAvalon_readData = VL_RANDOM_I(32); - top->dBusAvalon_response = VL_RANDOM_I(2); //TODO + top->dBusAvalon_readData = VL_RANDOM_I_WIDTH(32); + top->dBusAvalon_response = VL_RANDOM_I_WIDTH(2); //TODO } - top->dBusAvalon_waitRequestn = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1); + top->dBusAvalon_waitRequestn = (ws->dStall ? VL_RANDOM_I_WIDTH(7) < 100 : 1); } }; #endif @@ -3008,9 +3010,9 @@ public: top->debug_bus_cmd_payload_data = task.data; }else { top->debug_bus_cmd_valid = 0; - top->debug_bus_cmd_payload_wr = VL_RANDOM_I(1); - top->debug_bus_cmd_payload_address = VL_RANDOM_I(8); - top->debug_bus_cmd_payload_data = VL_RANDOM_I(32); + top->debug_bus_cmd_payload_wr = VL_RANDOM_I_WIDTH(1); + top->debug_bus_cmd_payload_address = VL_RANDOM_I_WIDTH(8); + top->debug_bus_cmd_payload_data = VL_RANDOM_I_WIDTH(32); } } }; @@ -3059,8 +3061,8 @@ public: }else { top->debugBusAvalon_write = 0; top->debugBusAvalon_read = 0; - top->debugBusAvalon_address = VL_RANDOM_I(8); - top->debugBusAvalon_writeData = VL_RANDOM_I(32); + top->debugBusAvalon_address = VL_RANDOM_I_WIDTH(8); + top->debugBusAvalon_writeData = VL_RANDOM_I_WIDTH(32); } } }; @@ -3373,7 +3375,7 @@ public: uint32_t readCmd(uint32_t size, uint32_t address){ - accessCmd(false, 2, address, VL_RANDOM_I(32)); + accessCmd(false, 2, address, VL_RANDOM_I_WIDTH(32)); int error; if((error = recv(clientSocket, buffer, 4, 0)) != 4){ printf("Should read 4 bytes, had %d", error); @@ -4434,7 +4436,7 @@ int main(int argc, char **argv, char **env) { } while(tasks.size() > FREERTOS_COUNT){ - tasks.erase(tasks.begin() + (VL_RANDOM_I(32)%tasks.size())); + tasks.erase(tasks.begin() + (VL_RANDOM_I_WIDTH(32)%tasks.size())); } @@ -4465,7 +4467,7 @@ int main(int argc, char **argv, char **env) { } while(tasks.size() > ZEPHYR_COUNT){ - tasks.erase(tasks.begin() + (VL_RANDOM_I(32)%tasks.size())); + tasks.erase(tasks.begin() + (VL_RANDOM_I_WIDTH(32)%tasks.size())); } From 378c0f87233c3808932eb9a2eeda1929c2d599be Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 4 Feb 2022 16:20:43 +0100 Subject: [PATCH 09/11] verilator++ --- .github/workflows/scala.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml index 2d4547f..859c137 100644 --- a/.github/workflows/scala.yml +++ b/.github/workflows/scala.yml @@ -40,7 +40,7 @@ jobs: with: path: | ~/tools - key: ${{ runner.os }}-tools_v2 + key: ${{ runner.os }}-tools_v3 - name: Setup env run: echo "$HOME/tools/bin" >> $GITHUB_PATH From 4dd650736f4ecb0d59bfc4353954b802048b4029 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 4 Feb 2022 16:36:11 +0100 Subject: [PATCH 10/11] verilator++ --- .github/workflows/scala.yml | 2 +- tools.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml index 859c137..9d2d2aa 100644 --- a/.github/workflows/scala.yml +++ b/.github/workflows/scala.yml @@ -40,7 +40,7 @@ jobs: with: path: | ~/tools - key: ${{ runner.os }}-tools_v3 + key: ${{ runner.os }}-tools_v4 - name: Setup env run: echo "$HOME/tools/bin" >> $GITHUB_PATH diff --git a/tools.sh b/tools.sh index ebe0592..7ee6a59 100644 --- a/tools.sh +++ b/tools.sh @@ -6,7 +6,7 @@ install_verilator(){ unset VERILATOR_ROOT # For bash cd verilator git pull # Make sure we're up-to-date - git checkout v4.040 + git checkout v4.216 autoconf # Create ./configure script ./configure --prefix ~/tools make -j$(nproc) From 62c07670af07f89e9254ba089a121cee81530b0b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 5 Feb 2022 11:31:04 +0100 Subject: [PATCH 11/11] version++ --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 9bec947..19e9c35 100644 --- a/build.sbt +++ b/build.sbt @@ -1,4 +1,4 @@ -val spinalVersion = "1.6.2" +val spinalVersion = "1.6.3" lazy val root = (project in file(".")). settings(