diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala
index 3cd633b..4d9575e 100644
--- a/src/main/scala/vexriscv/TestsWorkspace.scala
+++ b/src/main/scala/vexriscv/TestsWorkspace.scala
@@ -64,7 +64,7 @@ object TestsWorkspace {
               wayCount = 1,
               addressWidth = 32,
               cpuDataWidth = 32,
-              memDataWidth = 32,
+              memDataWidth = 128,
               catchIllegalAccess = true,
               catchAccessFault = true,
               asyncTagMemory = false,
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index f4aa237..3a72603 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -149,7 +149,7 @@ object VexRiscvSmpClusterGen {
             wayCount = 1,
             addressWidth = 32,
             cpuDataWidth = 32,
-            memDataWidth = 32,
+            memDataWidth = 128,
             catchIllegalAccess = true,
             catchAccessFault = true,
             asyncTagMemory = false,
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 244c3a9..60add57 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -6,7 +6,9 @@ import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
 import spinal.lib.com.jtag.Jtag
 import spinal.lib._
 import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
+import spinal.lib.eda.bench.Bench
 import spinal.lib.misc.Clint
+import vexriscv.demo.smp.VexRiscvLitexSmpClusterOpenSbi.{cpuCount, parameter}
 import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
 import vexriscv.{VexRiscv, VexRiscvConfig}
 import vexriscv.plugin.{CsrPlugin, DBusCachedPlugin, DebugPlugin, IBusCachedPlugin}
@@ -157,6 +159,32 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
   val peripheralWishbone = peripheralArbiter.io.output.toWishbone()
   io.peripheral << peripheralWishbone
 }
+object VexRiscvLitexSmpClusterGen extends App {
+  val cpuCount = 4
+  val withStall = false
+
+  def parameter = VexRiscvLitexSmpClusterParameter(
+    cluster = VexRiscvSmpClusterParameter(
+      cpuConfigs = List.tabulate(cpuCount) { hartId =>
+        vexRiscvConfig(
+          hartId = hartId,
+          ioRange =  address => address.msb,
+          resetVector = 0
+        )
+      }
+    ),
+    liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
+    liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
+  )
+
+  def dutGen = VexRiscvLitexSmpCluster(
+    p = parameter,
+    debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
+  )
+
+  SpinalVerilog(Bench.compressIo(dutGen))
+
+}
 
 
 object VexRiscvLitexSmpClusterOpenSbi extends App{
@@ -180,7 +208,7 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
           )
         }
       ),
-      liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 32),
+      liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
       liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
     )