From 7c0f2dc713545b3421777f2542cf1bc9eb92d140 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 20 Oct 2018 12:39:20 +0200 Subject: [PATCH] Add SimpleBus object --- src/main/scala/vexriscv/demo/MuraxUtiles.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 9d1f044..213dc70 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -22,7 +22,9 @@ case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{ val data = Bits(config.dataWidth bits) } - +object SimpleBus{ + def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth)) +} case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave { val cmd = Stream(SimpleBusCmd(config)) val rsp = Flow(SimpleBusRsp(config))