From 7c19288648c1cf93daa5a6fe79e9f6a163dfbdbc Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Fri, 17 Nov 2017 20:10:46 +0100
Subject: [PATCH] Update Synthesis bench Update some synthesis results

---
 README.md                                     |  2 +-
 .../scala/vexriscv/demo/SynthesisBench.scala  | 30 +++++--------------
 2 files changed, 9 insertions(+), 23 deletions(-)

diff --git a/README.md b/README.md
index a8b2bc0..434dc0d 100644
--- a/README.md
+++ b/README.md
@@ -49,7 +49,7 @@ The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
 
 ```
 VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) ->
-  Artix 7    -> 372 Mhz 568 LUT 603 FF 
+  Artix 7    -> 346 Mhz 481 LUT 539 FF
   Cyclone V  -> 201 Mhz 347 ALMs
   Cyclone IV -> 190 Mhz 673 LUT 529 FF 
   Cyclone II -> 154 Mhz 673 LUT 528 FF 
diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index 1e7238e..c4ce3a8 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -49,7 +49,6 @@ object VexRiscvSynthesisBench {
     val targets = XilinxStdTargets(
       vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
     ) ++ AlteraStdTargets(
-      quartusCycloneIIPath = null,
       quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
       quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin"
     )
@@ -72,28 +71,16 @@ object BrieySynthesisBench {
     }
 
 
-
     val rtls = List(briey)
 
-//    val targets = XilinxStdTargets(
-//      vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
-//    ) ++ AlteraStdTargets(
-//      quartusCycloneIIPath = null,
-//      quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
-//      quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin"
-//    )
-//
-//    Bench(rtls, targets, "/eda/tmp/")
-
     val targets = XilinxStdTargets(
-      vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
+      vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
     ) ++ AlteraStdTargets(
-      quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64",
-      quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64",
-      quartusCycloneVPath  = "D:/altera_lite/15.1/quartus/bin64"
+      quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/",
+      quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin/"
     )
 
-    Bench(rtls, targets, "E:/tmp/")
+    Bench(rtls, targets, "/eda/tmp/")
   }
 }
 
@@ -126,13 +113,12 @@ object MuraxSynthesisBench {
     val rtls = List(murax, muraxFast)
 
     val targets = XilinxStdTargets(
-      vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
+      vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
     ) ++ AlteraStdTargets(
-      quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64",
-      quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64",
-      quartusCycloneVPath  = "D:/altera_lite/15.1/quartus/bin64"
+      quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/",
+      quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin/"
     )
 
-    Bench(rtls, targets, "E:/tmp/")
+    Bench(rtls, targets, "/eda/tmp/")
   }
 }
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