diff --git a/build.sbt b/build.sbt
index d26c390..55aaa85 100644
--- a/build.sbt
+++ b/build.sbt
@@ -9,8 +9,8 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.2",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.2",
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.3",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.3",
   "org.yaml" % "snakeyaml" % "1.8"
 )
 
diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala
index 61bedaa..d72c456 100644
--- a/src/test/scala/vexriscv/MuraxSim.scala
+++ b/src/test/scala/vexriscv/MuraxSim.scala
@@ -4,16 +4,18 @@ import spinal.sim._
 import spinal.core._
 import spinal.core.sim._
 import vexriscv.demo.{Murax, MuraxConfig}
-
 import java.awt.Graphics
 import javax.swing.{JFrame, JPanel}
 
+import spinal.lib.com.jtag.sim.JtagTcp
+import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
+
 
 
 object MuraxSim {
   def main(args: Array[String]): Unit = {
 //    val config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
-    val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
+    val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "/home/spinalvm/hdl/VexRiscv/src/main/ressource/hex/muraxDemo.hex")
 
     SimConfig(new Murax(config)).allOptimisation.doManagedSim{dut =>
       val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
@@ -38,14 +40,14 @@ object MuraxSim {
           cycleCounter += 1
           if(cycleCounter == 100000){
             val currentTime = System.nanoTime()
-            println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz")
+//            println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz")
             lastTime = currentTime
             cycleCounter = 0
           }
         }
       }
 
-      val tcpJtag = TcpJtag(
+      val tcpJtag = JtagTcp(
         jtag = dut.io.jtag,
         jtagClkPeriod = jtagClkPeriod
       )
diff --git a/src/test/scala/vexriscv/TcpJtag.scala b/src/test/scala/vexriscv/TcpJtag.scala
deleted file mode 100644
index 89cec08..0000000
--- a/src/test/scala/vexriscv/TcpJtag.scala
+++ /dev/null
@@ -1,43 +0,0 @@
-package vexriscv
-
-import java.io.{InputStream, OutputStream}
-import java.net.ServerSocket
-
-import spinal.core.sim._
-import spinal.lib.com.jtag.Jtag
-
-import scala.concurrent.Future
-import scala.concurrent.ExecutionContext.Implicits.global
-
-object TcpJtag {
-  def apply(jtag: Jtag, jtagClkPeriod: Long) = fork {
-    var inputStream: InputStream = null
-    var outputStream: OutputStream = null
-
-    val server = Future {
-      val socket = new ServerSocket(7894)
-      println("WAITING FOR TCP JTAG CONNECTION")
-      while (true) {
-        val connection = socket.accept()
-        connection.setTcpNoDelay(true)
-        outputStream = connection.getOutputStream()
-        inputStream = connection.getInputStream()
-        println("TCP JTAG CONNECTION")
-      }
-    }
-
-    while (true) {
-      sleep(jtagClkPeriod * 200)
-      while (inputStream != null && inputStream.available() != 0) {
-        val buffer = inputStream.read()
-        jtag.tms #= (buffer & 1) != 0;
-        jtag.tdi #= (buffer & 2) != 0;
-        jtag.tck #= (buffer & 8) != 0;
-        if ((buffer & 4) != 0) {
-          outputStream.write(if (jtag.tdo.toBoolean) 1 else 0)
-        }
-        sleep(jtagClkPeriod / 2)
-      }
-    }
-  }
-}
diff --git a/src/test/scala/vexriscv/UartDecoder.scala b/src/test/scala/vexriscv/UartDecoder.scala
deleted file mode 100644
index 4b8558e..0000000
--- a/src/test/scala/vexriscv/UartDecoder.scala
+++ /dev/null
@@ -1,29 +0,0 @@
-package vexriscv
-
-import spinal.sim._
-import spinal.core.sim._
-import spinal.core.{Bool, assert}
-
-object UartDecoder {
-  def apply(uartPin : Bool, baudPeriod : Long) = fork{
-    waitUntil(uartPin.toBoolean == true)
-
-    while(true) {
-      waitUntil(uartPin.toBoolean == false)
-      sleep(baudPeriod/2)
-
-      assert(uartPin.toBoolean == false)
-      sleep(baudPeriod)
-
-      var buffer = 0
-      (0 to 7).suspendable.foreach{ bitId =>
-        if(uartPin.toBoolean)
-          buffer |= 1 << bitId
-        sleep(baudPeriod)
-      }
-
-      assert(uartPin.toBoolean == true)
-      print(buffer.toChar)
-    }
-  }
-}
diff --git a/src/test/scala/vexriscv/UartEncoder.scala b/src/test/scala/vexriscv/UartEncoder.scala
deleted file mode 100644
index c6cf1ce..0000000
--- a/src/test/scala/vexriscv/UartEncoder.scala
+++ /dev/null
@@ -1,28 +0,0 @@
-package vexriscv
-
-import spinal.sim._
-import spinal.core.sim._
-import spinal.core.Bool
-
-object UartEncoder {
-  def apply(uartPin : Bool, baudPeriod : Long) = fork{
-    uartPin #= true
-    while(true) {
-      if(System.in.available() != 0){
-        val buffer = System.in.read()
-        uartPin #= false
-        sleep(baudPeriod)
-
-        (0 to 7).suspendable.foreach{ bitId =>
-          uartPin #= ((buffer >> bitId) & 1) != 0
-          sleep(baudPeriod)
-        }
-
-        uartPin #= true
-        sleep(baudPeriod)
-      } else {
-        sleep(baudPeriod * 10)
-      }
-    }
-  }
-}