diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
index 9bd8d94..723ea7d 100644
--- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
+++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -25,7 +25,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
   val debugClockDomain = Handle[ClockDomain]
   val debugReset = Handle[Bool]
   val debugAskReset = Handle[() => Unit]
-  val hardwareBreakpointCount = Handle(0)
+  val hardwareBreakpointCount = Handle.sync(0)
 
   val iBus, dBus = Handle[Bmb]