From 807aa98d37f3f213630ada44df6115ffee3c6345 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Thu, 10 Feb 2022 19:55:08 +0100 Subject: [PATCH] plugin: DBusSimplePlugin: Remove assert This assert triggered sometimes at the beginning of a simulation. Since it's not really needed anymore, we can remove it. Signed-off-by: Daniel Schultz --- src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 094de17..372cfcc 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -518,9 +518,6 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, } } - - - if(rspStage != execute) assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") } //Reformat read responses, REGFILE_WRITE_DATA overriding