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VexRiscv
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with no bus stall, pass all tests except uniqueness

This commit is contained in:
Dolu1990 2017-11-06 20:26:45 +01:00
parent e2a432eb5e
commit 8098a03a9b
1 changed files with 7 additions and 2 deletions
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9
src/main/scala/vexriscv/demo/FormalSimple.scala
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@ -38,7 +38,7 @@ object FormalSimple extends App{
separatedAddSub = false,
executeInsertion = false
),
new LightShifterPlugin,
new FullBarrielShifterPlugin,
new HazardSimplePlugin(
bypassExecute = false,
bypassMemory = false,
@ -57,5 +57,10 @@ object FormalSimple extends App{
)
)
)
SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = spinal.core.SYNC)).generateVerilog(cpu())
SpinalConfig(
defaultConfigForClockDomains = ClockDomainConfig(
resetKind = spinal.core.SYNC,
resetActiveLevel = spinal.core.HIGH
)
).generateVerilog(cpu())
}