From 8098a03a9b4630f9a46c53db688a8d2e910353fd Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Mon, 6 Nov 2017 20:26:45 +0100
Subject: [PATCH] with no bus stall, pass all tests except uniqueness

---
 src/main/scala/vexriscv/demo/FormalSimple.scala | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/FormalSimple.scala b/src/main/scala/vexriscv/demo/FormalSimple.scala
index abb4d1f..39d1302 100644
--- a/src/main/scala/vexriscv/demo/FormalSimple.scala
+++ b/src/main/scala/vexriscv/demo/FormalSimple.scala
@@ -38,7 +38,7 @@ object FormalSimple extends App{
           separatedAddSub = false,
           executeInsertion = false
         ),
-        new LightShifterPlugin,
+        new FullBarrielShifterPlugin,
         new HazardSimplePlugin(
           bypassExecute           = false,
           bypassMemory            = false,
@@ -57,5 +57,10 @@ object FormalSimple extends App{
       )
     )
   )
-  SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = spinal.core.SYNC)).generateVerilog(cpu())
+  SpinalConfig(
+    defaultConfigForClockDomains = ClockDomainConfig(
+      resetKind = spinal.core.SYNC,
+      resetActiveLevel = spinal.core.HIGH
+    )
+  ).generateVerilog(cpu())
 }