diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index 202b4a0..1530d2a 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -47,14 +47,14 @@ object VexRiscvSynthesisBench {
     val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, fullNoMmu, full)
 
     val targets = XilinxStdTargets(
-      vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
+      vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
     ) ++ AlteraStdTargets(
-      quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64",
-      quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64",
-      quartusCycloneVPath  = "D:/altera_lite/15.1/quartus/bin64"
+      quartusCycloneIIPath = null,
+      quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
+      quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin"
     )
 
-    Bench(rtls, targets, "E:/tmp/")
+    Bench(rtls, targets, "/eda/tmp/")
   }
 }
 
@@ -75,6 +75,16 @@ object BrieySynthesisBench {
 
     val rtls = List(briey)
 
+//    val targets = XilinxStdTargets(
+//      vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
+//    ) ++ AlteraStdTargets(
+//      quartusCycloneIIPath = null,
+//      quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
+//      quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin"
+//    )
+//
+//    Bench(rtls, targets, "/eda/tmp/")
+    
     val targets = XilinxStdTargets(
       vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
     ) ++ AlteraStdTargets(
diff --git a/src/test/cpp/custom/simd_add/build/custom_simd_add.map b/src/test/cpp/custom/simd_add/build/custom_simd_add.map
index 453922b..4162b36 100644
--- a/src/test/cpp/custom/simd_add/build/custom_simd_add.map
+++ b/src/test/cpp/custom/simd_add/build/custom_simd_add.map
@@ -8,12 +8,12 @@ onChipRam        0x0000000000000000 0x0000000000002000 w !xr
 Linker script and memory map
 
 LOAD build/src/crt.o
-LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/libgcc.a
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/rv32i/ilp32/libgcc.a
 START GROUP
-LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/lib/libc.a
-LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/lib/libgloss.a
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
 END GROUP
-LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/libgcc.a
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/rv32i/ilp32/libgcc.a
                 0x0000000000000000                . = 0x0
 
 .crt_section    0x0000000000000000       0xd0
diff --git a/src/test/cpp/custom/simd_add/makefile b/src/test/cpp/custom/simd_add/makefile
index 16f4b92..49c9179 100644
--- a/src/test/cpp/custom/simd_add/makefile
+++ b/src/test/cpp/custom/simd_add/makefile
@@ -1,9 +1,9 @@
 PROJ_NAME=custom_simd_add
 
 
-RISCV_PATH=/opt/rv32i/
+RISCV_PATH=/opt/riscv/
 CFLAGS += -march=rv32i   -mabi=ilp32
-RISCV_NAME = riscv32-unknown-elf
+RISCV_NAME = riscv64-unknown-elf
 RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
 RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
 RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/