From 83232e986085f3a3570e427dcef59dcd53b8c543 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Wed, 15 Mar 2017 20:02:56 +0100
Subject: [PATCH] Faster pipeline arbitration logic (200 Mhz on cyclone IV c6)
 Branch plugin with jump in execute or memory stages (parameter)

---
 src/main/scala/SpinalRiscv/Pipeline.scala |  5 +----
 src/main/scala/SpinalRiscv/TopLevel.scala | 23 ++++++++++++++++-------
 2 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/SpinalRiscv/Pipeline.scala b/src/main/scala/SpinalRiscv/Pipeline.scala
index ec4db4c..4234559 100644
--- a/src/main/scala/SpinalRiscv/Pipeline.scala
+++ b/src/main/scala/SpinalRiscv/Pipeline.scala
@@ -108,15 +108,12 @@ trait Pipeline {
       val stageBefore = stages(stageIndex - 1)
       val stage = stages(stageIndex)
 
-      when(!stage.arbitration.isStuck) {
+      when(!stage.arbitration.isStuck || stage.arbitration.removeIt) {
         stage.arbitration.isValid := False
       }
       when(!stageBefore.arbitration.isStuck && !stageBefore.arbitration.removeIt) {
         stage.arbitration.isValid := stageBefore.arbitration.isValid
       }
-      when(stage.arbitration.removeIt){
-        stage.arbitration.isValid := False
-      }
     }
   }
 
diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/SpinalRiscv/TopLevel.scala
index cb9eb8b..7606fab 100644
--- a/src/main/scala/SpinalRiscv/TopLevel.scala
+++ b/src/main/scala/SpinalRiscv/TopLevel.scala
@@ -257,6 +257,7 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
     offset = 0
     stageables.foreach(e => {
       insert(e).assignFromBits(decodedBits(offset, e.dataType.getBitsWidth bits))
+//      insert(e).assignFromBits(RegNext(decodedBits(offset, e.dataType.getBitsWidth bits)))
       offset += e.dataType.getBitsWidth
     })
   }
@@ -273,13 +274,14 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
   }
 }
 
-class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
+class NoPredictionBranchPlugin(earlyBranch : Boolean) extends Plugin[VexRiscv]{
   object BranchCtrlEnum extends SpinalEnum(binarySequential){
     val INC,B,JAL,JALR = newElement()
   }
 
   object BRANCH_CTRL extends Stageable(BranchCtrlEnum())
   object BRANCH_SOLVED extends Stageable(BranchCtrlEnum())
+  object BRANCH_CALC extends Stageable(UInt(32 bits))
 
   var jumpInterface : Flow[UInt] = null
 
@@ -345,17 +347,24 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
       )
 
       val imm = IMM(input(INSTRUCTION))
-      jumpInterface.valid := arbitration.isFiring && input(BRANCH_SOLVED) =/= BranchCtrlEnum.INC
-      jumpInterface.payload := input(BRANCH_SOLVED).mux(
+      insert(BRANCH_CALC) := input(BRANCH_SOLVED).mux(
         BranchCtrlEnum.JAL  -> (input(PC)          + imm.j_sext.asUInt),
         BranchCtrlEnum.JALR -> (input(REG1).asUInt + imm.i_sext.asUInt),
         default             -> (input(PC)          + imm.b_sext.asUInt)    //B
       )
+    }
 
-      when(jumpInterface.valid){
+    val branchStage = if(earlyBranch) execute else memory
+    branchStage plug new Area {
+      import branchStage._
+      jumpInterface.valid := arbitration.isFiring && input(BRANCH_SOLVED) =/= BranchCtrlEnum.INC
+      jumpInterface.payload := input(BRANCH_CALC)
+
+      when(jumpInterface.valid) {
         prefetch.arbitration.removeIt := True
-        fetch.arbitration.removeIt    := True
-        decode.arbitration.removeIt   := True
+        fetch.arbitration.removeIt := True
+        decode.arbitration.removeIt := True
+        if(!earlyBranch) execute.arbitration.removeIt := True
       }
     }
   }
@@ -940,7 +949,7 @@ object TopLevel {
         new DBusSimplePlugin,
         //        new HazardSimplePlugin(true,true,true,true),
         new HazardSimplePlugin(false, false, false, false),
-        new NoPredictionBranchPlugin
+        new NoPredictionBranchPlugin(false)
       )
 
       val toplevel = new VexRiscv(config)