Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix CsrPlugin FPU access

This commit is contained in:
Dolu1990 2024-09-20 15:40:36 +02:00
parent 8c1e69b872
commit 83606a9eb0
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -766,7 +766,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
buffer.ready := injectionPort.fire
val fpu = withDebugFpuAccess generate new Area {
val access = service(classOf[FpuPlugin]).access
access.start := buffer.valid && buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE
access.start := buffer.valid && (buffer.op === DebugDmToHartOp.REG_READ || buffer.op === DebugDmToHartOp.REG_WRITE)
access.regId := buffer.address
access.write := buffer.op === DebugDmToHartOp.REG_WRITE
access.writeData := dataCsrw.value.take(2).asBits