From 861df664cf0f6a29196b6642445461fe95dc4283 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 8 Apr 2020 18:48:01 +0200
Subject: [PATCH] clean some AMO stuff

---
 src/main/scala/vexriscv/ip/DataCache.scala            | 7 ++++---
 src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 85d7d0c..d0a536b 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -629,6 +629,7 @@ class DataCache(p : DataCacheConfig) extends Component{
     if(withExternalLrSc) io.mem.cmd.exclusive := request.isLrsc || (if(withAmo) request.isAmo else False)
 
     val bypassCache = mmuRsp.isIoAccess || (if(withExternalLrSc) request.isLrsc else False)
+    val isAmoCached = if(withInternalAmo) isAmo else False
 
     when(io.cpu.writeBack.isValid) {
       when(bypassCache) {
@@ -646,7 +647,7 @@ class DataCache(p : DataCacheConfig) extends Component{
           io.cpu.writeBack.haltIt := False
         }
       } otherwise {
-        when(waysHit || request.wr && !isAmo) {   //Do not require a cache refill ?
+        when(waysHit || request.wr && !isAmoCached) {   //Do not require a cache refill ?
           cpuWriteToCache := True
 
           //Write through
@@ -655,7 +656,7 @@ class DataCache(p : DataCacheConfig) extends Component{
           io.mem.cmd.length := 0
           io.cpu.writeBack.haltIt clearWhen(!request.wr || io.mem.cmd.ready)
 
-          if(withAmo) when(isAmo){
+          if(withInternalAmo) when(isAmo){
             when(!internalAmo.resultRegValid) {
               io.mem.cmd.valid := False
               dataWriteCmd.valid := False
@@ -664,7 +665,7 @@ class DataCache(p : DataCacheConfig) extends Component{
           }
 
           //On write to read dataColisions
-          when((!request.wr || isAmo) && (dataColisions & waysHits) =/= 0){
+          when((!request.wr || isAmoCached) && (dataColisions & waysHits) =/= 0){
             io.cpu.redo := True
             if(withAmo) io.mem.cmd.valid := False
           }
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 0d7c930..3a13a7c 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -213,7 +213,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         val ff = input(INSTRUCTION)(31 downto 20).as(FenceFlags())
         if(withWriteResponse){
           hazard setWhen(input(MEMORY_FENCE) && (ff.PS && ff.SL)) //Manage write to read hit ordering (ensure invalidation timings)
-//          Not required as LR SC AMO naturaly enforce ordering
+//          Not required as LR SC AMO emited on the memory bus enforce the ordering, + it bypass the cache
 //          when(input(INSTRUCTION)(26 downto 25) =/= 0){
 //            if(withLrSc) hazard setWhen(input(MEMORY_LRSC))
 //            if(withAmo)  hazard setWhen(input(MEMORY_AMO))