From 8643086fc07fde798d31e66bd44f30c62a9f43f3 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 19 Jul 2017 18:34:16 +0200
Subject: [PATCH] Add Briey area and timings into readme

---
 README.md                                     | 14 ++++++---
 .../scala/VexRiscv/demo/SynthesisBench.scala  | 31 ++++++++++++++++++-
 2 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/README.md b/README.md
index e6b9a55..d0b1bf8 100644
--- a/README.md
+++ b/README.md
@@ -55,14 +55,14 @@ VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass) ->
   Cyclone II -> 144 Mhz 844 LUT 578 FF 
   
 VexRiscv small and productive (RV32I, 0.78 DMIPS/Mhz)  ->
-  Artix 7 -> 330 Mhz 719 LUT 557 FF 
-  Cyclone V -> 153 Mhz 539 ALMs
+  Artix 7   -> 330 Mhz 719 LUT 557 FF 
+  Cyclone V  -> 153 Mhz 539 ALMs
   Cyclone IV -> 148 Mhz 1,127 LUT 552 FF 
   Cyclone II -> 114 Mhz 1,133 LUT 551 FF 
 
 VexRiscv full no cache (RV32IM, 1.14 DMIPS/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
-  Artix 7 -> 291 Mhz 1403 LUT 936 FF 
-  Cyclone V -> 147 Mhz 928 ALMs
+  Artix 7    -> 291 Mhz 1403 LUT 936 FF 
+  Cyclone V  -> 147 Mhz 928 ALMs
   Cyclone IV -> 137 Mhz 1,910 LUT 959 FF 
   Cyclone II -> 110 Mhz 1,940 LUT 958 FF 
 
@@ -197,6 +197,12 @@ You can find multiples software examples and demo there : https://github.com/Spi
 
 You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing
 
+There is some measurements of Briey SoC timings and area : 
+  Artix 7    -> 230 Mhz 3551 LUT 3612 FF 
+  Cyclone V  -> 126 Mhz 2,608 ALMs
+  Cyclone IV -> 117 Mhz 5,196 LUT 3,784 FF 
+  Cyclone II -> 102 Mhz 5,321 LUT 3,787 FF 
+
 ## Build the RISC-V GCC
 
 To install in /opt/ the rv32i and rv32im gcc, do the following (will take hours):
diff --git a/src/main/scala/VexRiscv/demo/SynthesisBench.scala b/src/main/scala/VexRiscv/demo/SynthesisBench.scala
index 57df972..5bb2ad7 100644
--- a/src/main/scala/VexRiscv/demo/SynthesisBench.scala
+++ b/src/main/scala/VexRiscv/demo/SynthesisBench.scala
@@ -6,7 +6,7 @@ import spinal.lib.eda.bench.{XilinxStdTargets, Bench, AlteraStdTargets, Rtl}
 /**
  * Created by PIC32F_USER on 16/07/2017.
  */
-object SynthesisBench {
+object VexRiscvSynthesisBench {
   def main(args: Array[String]) {
     val smallestNoCsr = new Rtl {
       override def getName(): String = "VexRiscv smallest no CSR"
@@ -59,3 +59,32 @@ object SynthesisBench {
     Bench(rtls, targets, "E:/tmp/")
   }
 }
+
+
+object BrieySynthesisBench {
+  def main(args: Array[String]) {
+    val briey = new Rtl {
+      override def getName(): String = "Briey"
+      override def getRtlPath(): String = "Briey.v"
+      SpinalVerilog({
+        val briey = new Briey(BrieyConfig.default).setDefinitionName(getRtlPath().split("\\.").head)
+        briey.io.axiClk.setName("clk")
+        briey
+      })
+    }
+
+
+
+    val rtls = List(briey)
+
+    val targets = XilinxStdTargets(
+      vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
+    ) ++ AlteraStdTargets(
+      quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64",
+      quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64",
+      quartusCycloneVPath  = "D:/altera_lite/15.1/quartus/bin64"
+    )
+
+    Bench(rtls, targets, "E:/tmp/")
+  }
+}
\ No newline at end of file