From 8729530a8d74d84212c5e92d2a72ae9de7955ab6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 5 Jun 2018 02:33:18 +0200 Subject: [PATCH] Fix Dynamicfetch/!rvc config --- src/main/scala/vexriscv/plugin/Fetcher.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index ac7b6df..8edb6f8 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -487,7 +487,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val historyWrite = history.writePort val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush) - val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1)) + val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))) else True) //Avoid stoping instruction fetch in the middle patch if(compressedGen && cmdToRspStageCount == 1){