From 876222d886f9cde8acc5bdf9e55f9887641a2d10 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Tue, 14 Mar 2023 15:23:04 +0800 Subject: [PATCH] Fix FPU access port instanciation when not needed --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 7c2174b..fa80e78 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -645,7 +645,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep xretAwayFromMachine = False - if(pipeline.config.FLEN == 64) pipeline.service(classOf[FpuPlugin]).requireAccessPort() + if(withPrivilegedDebug && pipeline.config.FLEN == 64) pipeline.service(classOf[FpuPlugin]).requireAccessPort() injectionPort = withPrivilegedDebug generate pipeline.service(classOf[IBusFetcher]).getInjectionPort().setCompositeName(this, "injectionPort") debugMode = withPrivilegedDebug generate Bool().setName("debugMode") @@ -735,7 +735,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep bus.hartToDm.data := execute.input(SRC1) } - val withDebugFpuAccess = pipeline.config.FLEN == 64 + val withDebugFpuAccess = withPrivilegedDebug && pipeline.config.FLEN == 64 val dataCsrw = new Area{ val value = Vec.fill(1+withDebugFpuAccess.toInt)(Reg(Bits(32 bits)))