diff --git a/src/main/scala/vexriscv/plugin/FpuPlugin.scala b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
index 3e664f5..b3373e3 100644
--- a/src/main/scala/vexriscv/plugin/FpuPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
@@ -219,6 +219,9 @@ class FpuPlugin(externalFpu : Boolean = false,
       when(stages.last.arbitration.isFiring && stages.last.input(FPU_ENABLE) && stages.last.input(FPU_OPCODE) =/= FpuOpcode.STORE){
         fs := 3 //DIRTY
       }
+      when(List(CSR.FRM, CSR.FCSR, CSR.FFLAGS).map(id => service.isWriting(id)).orR){
+        fs := 3
+      }
 
       service.rw(CSR.SSTATUS, 13, fs)
       service.rw(CSR.MSTATUS, 13, fs)
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 3d61c9a..e5866fa 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -668,9 +668,9 @@ public:
 		case SATP: satp.raw = value;  break;
 
 		#ifdef RVF
-		case FCSR: fcsr.raw = value & 0x7F; break;
-		case FRM: fcsr.frm = value; break;
-		case FFLAGS: fcsr.flags = value; break;
+		case FCSR: fcsr.raw = value & 0x7F; status.fs = 3; break;
+		case FRM: fcsr.frm = value; status.fs = 3; break;
+		case FFLAGS: fcsr.flags = value; status.fs = 3; break;
 		#endif
 
 		default: ilegalInstruction(); return true; break;