From 888e1c0b8a3a59c724d73f3cd5be4bf56d2218f7 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 5 Apr 2019 01:08:57 +0200
Subject: [PATCH] Fix RVC instruction cache xtval allignement

---
 src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index ec1025c..1ecde55 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -207,7 +207,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
         if (catchSomething) {
           decodeExceptionPort.valid := False
           decodeExceptionPort.code.assignDontCare()
-          decodeExceptionPort.badAddr := cacheRsp.pc
+          decodeExceptionPort.badAddr := cacheRsp.pc(31 downto 2) @@ "00"
 
           if(catchIllegalAccess) when(cacheRsp.isValid && cacheRsp.mmuException && !issueDetected) {
             issueDetected \= True