diff --git a/README.md b/README.md index 0a01dbc..4ca3d96 100644 --- a/README.md +++ b/README.md @@ -20,76 +20,47 @@ The hardware description of this CPU is done by using an very software oriented - There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline. -## CPU instantiation -There is an example of instantiation of the CPU +## CPU generation +You can find two example of CPU instantiation in : +- src/main/scala/VexRiscv/GenFull.scala +- src/main/scala/VexRiscv/GenSmallest.scala -```scala -//Define the cpu configuraiton -val config = VexRiscvConfig( - pcWidth = 32 -) +To generate the corresponding RTL as a VexRiscv.v file, run : -//Define the CSR configuration (riscv-privileged-v1.9.1) -val csrConfig = MachineCsrConfig( - mvendorid = 11, - marchid = 22, - mimpid = 33, - mhartid = 0, - misaExtensionsInit = 66, - misaAccess = CsrAccess.READ_WRITE, - mtvecAccess = CsrAccess.READ_WRITE, - mtvecInit = 0x00000020l, - mepcAccess = CsrAccess.READ_WRITE, - mscratchGen = true, - mcauseAccess = CsrAccess.READ_WRITE, - mbadaddrAccess = CsrAccess.READ_WRITE, - mcycleAccess = CsrAccess.READ_WRITE, - minstretAccess = CsrAccess.READ_WRITE, - ecallGen = true, - wfiGen = true -) +```sh +sbt run-main VexRiscv.GenFull -//Add plugins into the cpu configuration -config.plugins ++= List( - new PcManagerSimplePlugin(0x00000000l, false), - new IBusSimplePlugin( - interfaceKeepData = true - ), - new DecoderSimplePlugin( - catchIllegalInstruction = true - ), - new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, - zeroBoot = false - ), - new IntAluPlugin, - new SrcPlugin, - new FullBarrielShifterPlugin, - new DBusSimplePlugin( - catchUnalignedException = true - ), - new HazardSimplePlugin(true, true, true, true), - new MulPlugin, - new DivPlugin, - new MachineCsr(csrConfig), - new BranchPlugin( - earlyBranch = false, - catchUnalignedException = true, - prediction = DYNAMIC - ) -) +# or +sbt run-main VexRiscv.GenSmallest +``` -//Instanciate the CPU -val toplevel = new VexRiscv(config) +## Tests +To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run : + +```sh +# To test the GenFull CPU +make clean run + +# To test the GenSmallest CPU +make clean run IBUS=IBUS_SIMPLE DBUS=DBUS_SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no +``` + +## Interactive debug of the simulated CPU via GDB/OpenOCD in Verilator +It's as described to run tests, but you just have to add DEBUG_PLUGIN_EXTERNAL=yes in the make arguments. +Work for the GenFull, but not for the GenSmallest as this configuration has no debug module. + +Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a GDB server connected to the target (the simulated CPU) + +```sh +src/openocd -c "set VEXRISCV_YAML PATH_TO_THE_GENERATED_CPU0_YAML_FILE" -f tcl/target/vexriscv_sim.cfg ``` -## Plugin structure +## Cpu plugin structure There is an example of an pseudo ALU plugin : ```scala - //Define an signal name/type which could be used in the pipeline object ALU_ENABLE extends Stageable(Bool) object ALU_OP extends Stageable(Bits(2 bits)) // ADD, SUB, AND, OR diff --git a/cpu0.yaml b/cpu0.yaml deleted file mode 100644 index 2569474..0000000 --- a/cpu0.yaml +++ /dev/null @@ -1,40 +0,0 @@ -dBus: !!SpinalRiscv.BusReport - flushInstructions: [147, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, - 33587347, 1879101455] - info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096} - kind: cached -iBus: !!SpinalRiscv.BusReport - flushInstructions: [16399] - info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096} - kind: cached diff --git a/src/main/scala/VexRiscv/GenFull.scala b/src/main/scala/VexRiscv/GenFull.scala new file mode 100644 index 0000000..131780f --- /dev/null +++ b/src/main/scala/VexRiscv/GenFull.scala @@ -0,0 +1,93 @@ +package VexRiscv + +import VexRiscv.Plugin._ +import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} +import spinal.core._ + +/** + * Created by spinalvm on 15.06.17. + */ +object GenFull extends App{ + SpinalVerilog( + gen = new VexRiscv( + config = VexRiscvConfig( + plugins = List( + new PcManagerSimplePlugin(0x00000000l, false), + new IBusCachedPlugin( + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine =32, + wayCount = 1, + wrappedMemAccess = true, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + catchMemoryTranslationMiss = true, + asyncTagMemory = false, + twoStageLogic = true + ), + askMemoryTranslation = true, + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 4 + ) + ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true, + catchMemoryTranslationMiss = true + ), + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 6 + ) + ), + new MemoryTranslatorPlugin( + tlbSize = 32, + virtualRange = _(31 downto 28) === 0xC, + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false + ), + new FullBarrielShifterPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new MulPlugin, + new DivPlugin, + new CsrPlugin(CsrPluginConfig.all), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true, + prediction = DYNAMIC + ), + new YamlPlugin("cpu0.yaml") + ) + ) + ) + ) +} diff --git a/src/main/scala/VexRiscv/GenSmallest.scala b/src/main/scala/VexRiscv/GenSmallest.scala new file mode 100644 index 0000000..db92673 --- /dev/null +++ b/src/main/scala/VexRiscv/GenSmallest.scala @@ -0,0 +1,56 @@ +package VexRiscv + +import VexRiscv.Plugin._ +import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} +import spinal.core._ + +/** + * Created by spinalvm on 15.06.17. + */ +object GenSmallest extends App{ + SpinalVerilog( + gen = new VexRiscv( + config = VexRiscvConfig( + plugins = List( + new PcManagerSimplePlugin(0x00000000l, true), + new IBusSimplePlugin( + interfaceKeepData = false, + catchAccessFault = false + ), + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false + ), + new CsrPlugin(CsrPluginConfig.smallest), + new DecoderSimplePlugin( + catchIllegalInstruction = false + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false + ), + new LightShifterPlugin, + new HazardSimplePlugin( + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = false, + prediction = NONE + ), + new YamlPlugin("cpu0.yaml") + ) + ) + ) + ) +} diff --git a/src/main/scala/SpinalRiscv/Pipeline.scala b/src/main/scala/VexRiscv/Pipeline.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Pipeline.scala rename to src/main/scala/VexRiscv/Pipeline.scala index b627767..1879e50 100644 --- a/src/main/scala/SpinalRiscv/Pipeline.scala +++ b/src/main/scala/VexRiscv/Pipeline.scala @@ -1,6 +1,6 @@ -package SpinalRiscv +package VexRiscv -import SpinalRiscv.Plugin._ +import VexRiscv.Plugin._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala b/src/main/scala/VexRiscv/Plugin/BranchPlugin.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala rename to src/main/scala/VexRiscv/Plugin/BranchPlugin.scala index dfd7144..28bc51d 100644 --- a/src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/BranchPlugin.scala @@ -1,7 +1,7 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.Riscv._ -import SpinalRiscv._ +import VexRiscv.Riscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/CsrPlugin.scala b/src/main/scala/VexRiscv/Plugin/CsrPlugin.scala similarity index 88% rename from src/main/scala/SpinalRiscv/Plugin/CsrPlugin.scala rename to src/main/scala/VexRiscv/Plugin/CsrPlugin.scala index 105d59e..fee202b 100644 --- a/src/main/scala/SpinalRiscv/Plugin/CsrPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/CsrPlugin.scala @@ -1,9 +1,9 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin import spinal.core._ import spinal.lib._ -import SpinalRiscv._ -import SpinalRiscv.Riscv._ +import VexRiscv._ +import VexRiscv.Riscv._ import scala.collection.mutable.ArrayBuffer import scala.collection.mutable @@ -31,7 +31,7 @@ object CsrAccess { } case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int) -case class MachineCsrConfig( +case class csrPluginConfig( catchIllegalAccess : Boolean, mvendorid : BigInt, marchid : BigInt, @@ -54,7 +54,71 @@ case class MachineCsrConfig( assert(!ucycleAccess.canWrite) } +object CsrPluginConfig{ + val all = csrPluginConfig( + catchIllegalAccess = true, + mvendorid = 11, + marchid = 22, + mimpid = 33, + mhartid = 0, + misaExtensionsInit = 66, + misaAccess = CsrAccess.READ_WRITE, + mtvecAccess = CsrAccess.READ_WRITE, + mtvecInit = 0x00000020l, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = true, + mcauseAccess = CsrAccess.READ_WRITE, + mbadaddrAccess = CsrAccess.READ_WRITE, + mcycleAccess = CsrAccess.READ_WRITE, + minstretAccess = CsrAccess.READ_WRITE, + ecallGen = true, + wfiGen = true, + ucycleAccess = CsrAccess.READ_ONLY + ) + val small = csrPluginConfig( + catchIllegalAccess = false, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 66, + misaAccess = CsrAccess.NONE, + mtvecAccess = CsrAccess.NONE, + mtvecInit = 0x00000020l, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = false, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.READ_ONLY, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = false, + wfiGen = false, + ucycleAccess = CsrAccess.NONE + ) + + val smallest = csrPluginConfig( + catchIllegalAccess = false, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 66, + misaAccess = CsrAccess.NONE, + mtvecAccess = CsrAccess.NONE, + mtvecInit = 0x00000020l, + mepcAccess = CsrAccess.READ_ONLY, + mscratchGen = false, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.NONE, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = false, + wfiGen = false, + ucycleAccess = CsrAccess.NONE + ) + +} case class CsrWrite(that : Data, bitOffset : Int) case class CsrRead(that : Data , bitOffset : Int) case class CsrMapping(){ @@ -76,7 +140,7 @@ case class CsrMapping(){ -class CsrPlugin(config : MachineCsrConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor{ +class CsrPlugin(config : csrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor{ import config._ import CsrAccess._ diff --git a/src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala b/src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala rename to src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala index f9b9095..b6bb877 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala @@ -1,7 +1,7 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.ip._ -import SpinalRiscv._ +import VexRiscv.ip._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala rename to src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala index 4fe5d22..a811eb3 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi._ diff --git a/src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala b/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala similarity index 97% rename from src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala rename to src/main/scala/VexRiscv/Plugin/DebugPlugin.scala index 2f21411..c9ec045 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala @@ -1,8 +1,8 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.Plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL} -import SpinalRiscv._ -import SpinalRiscv.ip._ +import VexRiscv.Plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL} +import VexRiscv._ +import VexRiscv.ip._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba3.apb.{Apb3Config, Apb3} diff --git a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/DecoderSimplePlugin.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala rename to src/main/scala/VexRiscv/Plugin/DecoderSimplePlugin.scala index f1ece24..73af9ab 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DecoderSimplePlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/DivPlugin.scala b/src/main/scala/VexRiscv/Plugin/DivPlugin.scala similarity index 97% rename from src/main/scala/SpinalRiscv/Plugin/DivPlugin.scala rename to src/main/scala/VexRiscv/Plugin/DivPlugin.scala index 1605253..a866a2d 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DivPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DivPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.{VexRiscv, _} +import VexRiscv.{VexRiscv, _} import spinal.core._ import spinal.lib.math.MixedDivider diff --git a/src/main/scala/SpinalRiscv/Plugin/HazardPessimisticPlugin.scala b/src/main/scala/VexRiscv/Plugin/HazardPessimisticPlugin.scala similarity index 91% rename from src/main/scala/SpinalRiscv/Plugin/HazardPessimisticPlugin.scala rename to src/main/scala/VexRiscv/Plugin/HazardPessimisticPlugin.scala index 1fe0977..f688ff9 100644 --- a/src/main/scala/SpinalRiscv/Plugin/HazardPessimisticPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/HazardPessimisticPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/HazardSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/HazardSimplePlugin.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Plugin/HazardSimplePlugin.scala rename to src/main/scala/VexRiscv/Plugin/HazardSimplePlugin.scala index 477f55e..de2a752 100644 --- a/src/main/scala/SpinalRiscv/Plugin/HazardSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/HazardSimplePlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala b/src/main/scala/VexRiscv/Plugin/IBusCachedPlugin.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala rename to src/main/scala/VexRiscv/Plugin/IBusCachedPlugin.scala index 06c5887..a309706 100644 --- a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/IBusCachedPlugin.scala @@ -1,7 +1,7 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ -import SpinalRiscv.ip._ +import VexRiscv._ +import VexRiscv.ip._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/IBusSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala similarity index 97% rename from src/main/scala/SpinalRiscv/Plugin/IBusSimplePlugin.scala rename to src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala index 8ba71ee..0fcf68f 100644 --- a/src/main/scala/SpinalRiscv/Plugin/IBusSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv} +import VexRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv} import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi._ diff --git a/src/main/scala/SpinalRiscv/Plugin/IntAluPlugin.scala b/src/main/scala/VexRiscv/Plugin/IntAluPlugin.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Plugin/IntAluPlugin.scala rename to src/main/scala/VexRiscv/Plugin/IntAluPlugin.scala index 1d41535..406036e 100644 --- a/src/main/scala/SpinalRiscv/Plugin/IntAluPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/IntAluPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ object IntAluPlugin{ object AluBitwiseCtrlEnum extends SpinalEnum(binarySequential){ diff --git a/src/main/scala/SpinalRiscv/Plugin/MemoryTranslatorPlugin.scala b/src/main/scala/VexRiscv/Plugin/MemoryTranslatorPlugin.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Plugin/MemoryTranslatorPlugin.scala rename to src/main/scala/VexRiscv/Plugin/MemoryTranslatorPlugin.scala index 98d1916..810619d 100644 --- a/src/main/scala/SpinalRiscv/Plugin/MemoryTranslatorPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/MemoryTranslatorPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.{VexRiscv, _} +import VexRiscv.{VexRiscv, _} import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/MulPlugin.scala b/src/main/scala/VexRiscv/Plugin/MulPlugin.scala similarity index 97% rename from src/main/scala/SpinalRiscv/Plugin/MulPlugin.scala rename to src/main/scala/VexRiscv/Plugin/MulPlugin.scala index 832195f..ab96336 100644 --- a/src/main/scala/SpinalRiscv/Plugin/MulPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/MulPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin -import SpinalRiscv._ -import SpinalRiscv.VexRiscv +package VexRiscv.Plugin +import VexRiscv._ +import VexRiscv.VexRiscv import spinal.core._ class MulPlugin extends Plugin[VexRiscv]{ diff --git a/src/main/scala/SpinalRiscv/Plugin/PcManagerSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/PcManagerSimplePlugin.scala similarity index 97% rename from src/main/scala/SpinalRiscv/Plugin/PcManagerSimplePlugin.scala rename to src/main/scala/VexRiscv/Plugin/PcManagerSimplePlugin.scala index 280f83a..22f9b06 100644 --- a/src/main/scala/SpinalRiscv/Plugin/PcManagerSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/PcManagerSimplePlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/Plugin.scala b/src/main/scala/VexRiscv/Plugin/Plugin.scala similarity index 89% rename from src/main/scala/SpinalRiscv/Plugin/Plugin.scala rename to src/main/scala/VexRiscv/Plugin/Plugin.scala index 023a59e..3375757 100644 --- a/src/main/scala/SpinalRiscv/Plugin/Plugin.scala +++ b/src/main/scala/VexRiscv/Plugin/Plugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.{Pipeline, Stage} +import VexRiscv.{Pipeline, Stage} import spinal.core.Area /** diff --git a/src/main/scala/SpinalRiscv/Plugin/RegFilePlugin.scala b/src/main/scala/VexRiscv/Plugin/RegFilePlugin.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Plugin/RegFilePlugin.scala rename to src/main/scala/VexRiscv/Plugin/RegFilePlugin.scala index 30ac01b..26a4b82 100644 --- a/src/main/scala/SpinalRiscv/Plugin/RegFilePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/RegFilePlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala b/src/main/scala/VexRiscv/Plugin/ShiftPlugins.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala rename to src/main/scala/VexRiscv/Plugin/ShiftPlugins.scala index 7f7515a..c73d151 100644 --- a/src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala +++ b/src/main/scala/VexRiscv/Plugin/ShiftPlugins.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib.Reverse diff --git a/src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala b/src/main/scala/VexRiscv/Plugin/SrcPlugin.scala similarity index 96% rename from src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala rename to src/main/scala/VexRiscv/Plugin/SrcPlugin.scala index dbe9ef7..3a0b02a 100644 --- a/src/main/scala/SpinalRiscv/Plugin/SrcPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/SrcPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.{Riscv, VexRiscv} +import VexRiscv.{Riscv, VexRiscv} import spinal.core._ diff --git a/src/main/scala/SpinalRiscv/Plugin/StaticMemoryTranslatorPlugin.scala b/src/main/scala/VexRiscv/Plugin/StaticMemoryTranslatorPlugin.scala similarity index 95% rename from src/main/scala/SpinalRiscv/Plugin/StaticMemoryTranslatorPlugin.scala rename to src/main/scala/VexRiscv/Plugin/StaticMemoryTranslatorPlugin.scala index 6cd877b..05aa6cd 100644 --- a/src/main/scala/SpinalRiscv/Plugin/StaticMemoryTranslatorPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/StaticMemoryTranslatorPlugin.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin -import SpinalRiscv.{VexRiscv, _} +import VexRiscv.{VexRiscv, _} import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/Plugin/YamlPlugin.scala b/src/main/scala/VexRiscv/Plugin/YamlPlugin.scala similarity index 90% rename from src/main/scala/SpinalRiscv/Plugin/YamlPlugin.scala rename to src/main/scala/VexRiscv/Plugin/YamlPlugin.scala index b39eceb..121a08f 100644 --- a/src/main/scala/SpinalRiscv/Plugin/YamlPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/YamlPlugin.scala @@ -1,8 +1,8 @@ -package SpinalRiscv.Plugin +package VexRiscv.Plugin import java.util -import SpinalRiscv.{ReportService, VexRiscv} +import VexRiscv.{ReportService, VexRiscv} import org.yaml.snakeyaml.{DumperOptions, Yaml} diff --git a/src/main/scala/SpinalRiscv/Riscv.scala b/src/main/scala/VexRiscv/Riscv.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Riscv.scala rename to src/main/scala/VexRiscv/Riscv.scala index 89f8984..1b1af88 100644 --- a/src/main/scala/SpinalRiscv/Riscv.scala +++ b/src/main/scala/VexRiscv/Riscv.scala @@ -1,4 +1,4 @@ -package SpinalRiscv +package VexRiscv import spinal.core._ diff --git a/src/main/scala/SpinalRiscv/Services.scala b/src/main/scala/VexRiscv/Services.scala similarity index 98% rename from src/main/scala/SpinalRiscv/Services.scala rename to src/main/scala/VexRiscv/Services.scala index 20b5d4c..72890b3 100644 --- a/src/main/scala/SpinalRiscv/Services.scala +++ b/src/main/scala/VexRiscv/Services.scala @@ -1,4 +1,4 @@ -package SpinalRiscv +package VexRiscv import java.util diff --git a/src/main/scala/SpinalRiscv/Stage.scala b/src/main/scala/VexRiscv/Stage.scala similarity index 99% rename from src/main/scala/SpinalRiscv/Stage.scala rename to src/main/scala/VexRiscv/Stage.scala index 6966142..b3c4670 100644 --- a/src/main/scala/SpinalRiscv/Stage.scala +++ b/src/main/scala/VexRiscv/Stage.scala @@ -1,4 +1,4 @@ -package SpinalRiscv +package VexRiscv import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/VexRiscv/TestsWorkspace.scala similarity index 72% rename from src/main/scala/SpinalRiscv/TopLevel.scala rename to src/main/scala/VexRiscv/TestsWorkspace.scala index 60f2194..852e33c 100644 --- a/src/main/scala/SpinalRiscv/TopLevel.scala +++ b/src/main/scala/VexRiscv/TestsWorkspace.scala @@ -16,92 +16,16 @@ * License along with this library. */ -package SpinalRiscv +package VexRiscv -import SpinalRiscv.Plugin._ +import VexRiscv.Plugin._ import spinal.core._ import spinal.lib._ -import SpinalRiscv.ip._ +import VexRiscv.ip._ -object TopLevel { +object TestsWorkspace { def main(args: Array[String]) { SpinalVerilog { - - -// val iCacheConfig = InstructionCacheConfig( -// cacheSize =4096, -// bytePerLine =32, -// wayCount = 1, -// wrappedMemAccess = true, -// addressWidth = 32, -// cpuDataWidth = 32, -// memDataWidth = 32 -// ) - - - val csrConfigAll = MachineCsrConfig( - catchIllegalAccess = true, - mvendorid = 11, - marchid = 22, - mimpid = 33, - mhartid = 0, - misaExtensionsInit = 66, - misaAccess = CsrAccess.READ_WRITE, - mtvecAccess = CsrAccess.READ_WRITE, - mtvecInit = 0x00000020l, - mepcAccess = CsrAccess.READ_WRITE, - mscratchGen = true, - mcauseAccess = CsrAccess.READ_WRITE, - mbadaddrAccess = CsrAccess.READ_WRITE, - mcycleAccess = CsrAccess.READ_WRITE, - minstretAccess = CsrAccess.READ_WRITE, - ecallGen = true, - wfiGen = true, - ucycleAccess = CsrAccess.READ_ONLY - ) - - val csrConfigSmall = MachineCsrConfig( - catchIllegalAccess = false, - mvendorid = null, - marchid = null, - mimpid = null, - mhartid = null, - misaExtensionsInit = 66, - misaAccess = CsrAccess.NONE, - mtvecAccess = CsrAccess.NONE, - mtvecInit = 0x00000020l, - mepcAccess = CsrAccess.READ_WRITE, - mscratchGen = false, - mcauseAccess = CsrAccess.READ_ONLY, - mbadaddrAccess = CsrAccess.READ_ONLY, - mcycleAccess = CsrAccess.NONE, - minstretAccess = CsrAccess.NONE, - ecallGen = false, - wfiGen = false, - ucycleAccess = CsrAccess.NONE - ) - - val csrConfigSmallest = MachineCsrConfig( - catchIllegalAccess = false, - mvendorid = null, - marchid = null, - mimpid = null, - mhartid = null, - misaExtensionsInit = 66, - misaAccess = CsrAccess.NONE, - mtvecAccess = CsrAccess.NONE, - mtvecInit = 0x00000020l, - mepcAccess = CsrAccess.READ_ONLY, - mscratchGen = false, - mcauseAccess = CsrAccess.READ_ONLY, - mbadaddrAccess = CsrAccess.NONE, - mcycleAccess = CsrAccess.NONE, - minstretAccess = CsrAccess.NONE, - ecallGen = false, - wfiGen = false, - ucycleAccess = CsrAccess.NONE - ) - val configFull = VexRiscvConfig( plugins = List( new PcManagerSimplePlugin(0x00000000l, false), @@ -185,7 +109,7 @@ object TopLevel { // new HazardSimplePlugin(false, false, false, false), new MulPlugin, new DivPlugin, - new CsrPlugin(csrConfigAll), + new CsrPlugin(CsrPluginConfig.all), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = false, @@ -259,7 +183,7 @@ object TopLevel { catchAddressMisaligned = true, catchAccessFault = true ), - new CsrPlugin(csrConfigSmall), + new CsrPlugin(CsrPluginConfig.small), new DecoderSimplePlugin( catchIllegalInstruction = true ), @@ -298,10 +222,6 @@ object TopLevel { val toplevel = new VexRiscv(configFull) // val toplevel = new VexRiscv(configLight) // val toplevel = new VexRiscv(configTest) - toplevel.decode.input(toplevel.config.INSTRUCTION).addAttribute(Verilator.public) - toplevel.decode.input(toplevel.config.PC).addAttribute(Verilator.public) - toplevel.decode.arbitration.isValid.addAttribute(Verilator.public) - toplevel.decode.arbitration.haltIt.addAttribute(Verilator.public) // toplevel.writeBack.input(config.PC).addAttribute(Verilator.public) // toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel) diff --git a/src/main/scala/SpinalRiscv/VexRiscv.scala b/src/main/scala/VexRiscv/VexRiscv.scala similarity index 88% rename from src/main/scala/SpinalRiscv/VexRiscv.scala rename to src/main/scala/VexRiscv/VexRiscv.scala index 19b0909..c24b52a 100644 --- a/src/main/scala/SpinalRiscv/VexRiscv.scala +++ b/src/main/scala/VexRiscv/VexRiscv.scala @@ -1,6 +1,6 @@ -package SpinalRiscv +package VexRiscv -import SpinalRiscv.Plugin.Plugin +import VexRiscv.Plugin.Plugin import spinal.core._ import spinal.lib._ import scala.collection.mutable.ArrayBuffer @@ -56,6 +56,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ plugins ++= config.plugins //regression usage + decode.input(config.INSTRUCTION).addAttribute(Verilator.public) + decode.input(config.PC).addAttribute(Verilator.public) + decode.arbitration.isValid.addAttribute(Verilator.public) + decode.arbitration.haltIt.addAttribute(Verilator.public) writeBack.input(config.INSTRUCTION) keep() addAttribute(Verilator.public) writeBack.input(config.PC) keep() addAttribute(Verilator.public) writeBack.arbitration.isValid keep() addAttribute(Verilator.public) diff --git a/src/main/scala/SpinalRiscv/demo/Briey.scala b/src/main/scala/VexRiscv/demo/Briey.scala similarity index 98% rename from src/main/scala/SpinalRiscv/demo/Briey.scala rename to src/main/scala/VexRiscv/demo/Briey.scala index a10dc96..25f659f 100644 --- a/src/main/scala/SpinalRiscv/demo/Briey.scala +++ b/src/main/scala/VexRiscv/demo/Briey.scala @@ -1,9 +1,9 @@ -package SpinalRiscv.demo +package VexRiscv.demo -import SpinalRiscv.Plugin._ -import SpinalRiscv._ -import SpinalRiscv.ip.{DataCacheConfig, InstructionCacheConfig} +import VexRiscv.Plugin._ +import VexRiscv._ +import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba3.apb._ @@ -265,7 +265,7 @@ class Briey(config: BrieyConfig) extends Component{ prediction = STATIC ), new CsrPlugin( - config = MachineCsrConfig( + config = csrPluginConfig( catchIllegalAccess = false, mvendorid = null, marchid = null, diff --git a/src/main/scala/SpinalRiscv/ip/DataCache.scala b/src/main/scala/VexRiscv/ip/DataCache.scala similarity index 99% rename from src/main/scala/SpinalRiscv/ip/DataCache.scala rename to src/main/scala/VexRiscv/ip/DataCache.scala index e94ba36..5fbfdf5 100644 --- a/src/main/scala/SpinalRiscv/ip/DataCache.scala +++ b/src/main/scala/VexRiscv/ip/DataCache.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.ip +package VexRiscv.ip -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi.{Axi4Shared, Axi4Config} diff --git a/src/main/scala/SpinalRiscv/ip/InstructionCache.scala b/src/main/scala/VexRiscv/ip/InstructionCache.scala similarity index 99% rename from src/main/scala/SpinalRiscv/ip/InstructionCache.scala rename to src/main/scala/VexRiscv/ip/InstructionCache.scala index afd8c74..85b3ab0 100644 --- a/src/main/scala/SpinalRiscv/ip/InstructionCache.scala +++ b/src/main/scala/VexRiscv/ip/InstructionCache.scala @@ -1,6 +1,6 @@ -package SpinalRiscv.ip +package VexRiscv.ip -import SpinalRiscv._ +import VexRiscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi.{Axi4ReadOnly, Axi4Config} diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 9935f14..6d4a4fe 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -39,7 +39,12 @@ public: uint8_t* get(uint32_t address){ if(mem[address >> 20] == NULL) { uint8_t* ptr = new uint8_t[1024*1024]; - for(uint32_t i = 0;i < 1024*1024;i++) ptr[i] = 0xFF; + for(uint32_t i = 0;i < 1024*1024;i+=4) { + ptr[i + 0] = 0xFF; + ptr[i + 1] = 0xFF; + ptr[i + 2] = 0xFF; + ptr[i + 3] = 0xFF; + } mem[address >> 20] = ptr; } return &mem[address >> 20][address & 0xFFFFF]; @@ -223,7 +228,7 @@ public: virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error) { if(addr % 4 != 0) { cout << "Warning, unaligned IBusAccess : " << addr << endl; - fail(); + // fail(); } *data = ( (mem[addr + 0] << 0) | (mem[addr + 1] << 8) @@ -461,7 +466,7 @@ public: virtual void preCycle(){ if (top->iBus_cmd_valid && top->iBus_cmd_ready && !pending) { - assertEq(top->iBus_cmd_payload_pc & 3,0); + //assertEq(top->iBus_cmd_payload_pc & 3,0); pending = true; ws->iBusAccess(top->iBus_cmd_payload_pc,&inst_next,&error_next); } @@ -966,7 +971,7 @@ public: } }; - +#ifdef DEBUG_PLUGIN #include #include @@ -1137,6 +1142,7 @@ public: } }; +#endif string riscvTestMain[] = { "rv32ui-p-simple", @@ -1223,67 +1229,75 @@ int main(int argc, char **argv, char **env) { for(int idx = 0;idx < 1;idx++){ #ifndef REF - #ifdef DEBUG_PLUGIN_EXTERNAL - { - Workspace w("debugPluginExternal"); - w.loadHex("../../resources/hex/debugPluginExternal.hex"); - w.noInstructionReadCheck(); - #if defined(TRACE) || defined(TRACE_ACCESS) - w.setCyclesPerSecond(5e3); - printf("Speed reduced 5Khz\n"); + #ifdef DEBUG_PLUGIN_EXTERNAL + { + Workspace w("debugPluginExternal"); + w.loadHex("../../resources/hex/debugPluginExternal.hex"); + w.noInstructionReadCheck(); + #if defined(TRACE) || defined(TRACE_ACCESS) + w.setCyclesPerSecond(5e3); + printf("Speed reduced 5Khz\n"); + #endif + w.run(1e9); + } #endif - w.run(1e9); - } - #endif - TestA().run(); + TestA().run(); - for(const string &name : riscvTestMain){ - redo(REDO,RiscvTest(name).run();) - } - for(const string &name : riscvTestMemory){ - redo(REDO,RiscvTest(name).run();) - } - for(const string &name : riscvTestMul){ - redo(REDO,RiscvTest(name).run();) - } - for(const string &name : riscvTestDiv){ - redo(REDO,RiscvTest(name).run();) - } + for(const string &name : riscvTestMain){ + redo(REDO,RiscvTest(name).run();) + } + for(const string &name : riscvTestMemory){ + redo(REDO,RiscvTest(name).run();) + } + #ifdef MUL + for(const string &name : riscvTestMul){ + redo(REDO,RiscvTest(name).run();) + } + #endif + #ifdef DIV + for(const string &name : riscvTestDiv){ + redo(REDO,RiscvTest(name).run();) + } + #endif - #ifdef CSR - uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u , - 8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 }; - redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).noInstructionReadCheck()->run(4e3);) - #endif - #ifdef MMU - uint32_t mmuRef[] = {1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5, - 13, 0xC4000000,0x33333333, 6,7, - 1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5, - 13, 0xC4000000,0x33333333, 6,7}; - redo(REDO,TestX28("mmu",mmuRef, sizeof(mmuRef)/4).noInstructionReadCheck()->run(4e3);) - #endif + #ifdef CSR + uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u , + 8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 }; + redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).noInstructionReadCheck()->run(4e3);) + #endif + #ifdef MMU + uint32_t mmuRef[] = {1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5, + 13, 0xC4000000,0x33333333, 6,7, + 1,2,3, 0x11111111, 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x22222222, 4, 0x11111111, 0x33333333, 0x33333333, 5, + 13, 0xC4000000,0x33333333, 6,7}; + redo(REDO,TestX28("mmu",mmuRef, sizeof(mmuRef)/4).noInstructionReadCheck()->run(4e3);) + #endif #endif #ifdef DEBUG_PLUGIN - redo(REDO,DebugPluginTest().run(1e6);); + redo(REDO,DebugPluginTest().run(1e6);); #endif #ifdef DHRYSTONE - Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6); - Dhrystone("dhrystoneO3M_Stall","dhrystoneO3M",true,true).run(1.5e6); - Dhrystone("dhrystoneO3","dhrystoneO3",false,false).run(1.5e6); - Dhrystone("dhrystoneO3M","dhrystoneO3M",false,false).run(1.2e6); + Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6); + #if defined(MUL) || defined(DIV) + Dhrystone("dhrystoneO3M_Stall","dhrystoneO3M",true,true).run(1.5e6); + #endif + Dhrystone("dhrystoneO3","dhrystoneO3",false,false).run(1.5e6); + #if defined(MUL) || defined(DIV) + Dhrystone("dhrystoneO3M","dhrystoneO3M",false,false).run(1.2e6); + #endif #endif #ifdef FREE_RTOS - redo(1,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);) + redo(1,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);) #endif } diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index e749621..e153266 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -1,15 +1,17 @@ -IBUS=IBUS_CACHED -DBUS=DBUS_CACHED +IBUS?=IBUS_CACHED +DBUS?=DBUS_CACHED TRACE?=no TRACE_ACCESS?=no TRACE_START=0 -CSR=yes -MMU=yes -DEBUG_PLUGIN=yes +MUL?=yes +DIV?=yes +CSR?=yes +MMU?=yes +DEBUG_PLUGIN?=yes DEBUG_PLUGIN_EXTERNAL?=no DHRYSTONE=yes FREE_RTOS=no -REDO=10 +REDO?=10 REF=no TRACE_WITH_TIME=no REF_TIME=no @@ -45,6 +47,14 @@ ifeq ($(MMU),yes) ADDCFLAGS += -CFLAGS -DMMU endif +ifeq ($(MUL),yes) + ADDCFLAGS += -CFLAGS -DMUL +endif + +ifeq ($(DIV),yes) + ADDCFLAGS += -CFLAGS -DDIV +endif + ifeq ($(TRACE_ACCESS),yes) ADDCFLAGS += -CFLAGS -DTRACE_ACCESS endif