From 8968b5a3fafd52d1e88fc7b7ae0c7ba031d9d7b3 Mon Sep 17 00:00:00 2001
From: Marc Emery <marc.emery@amnis.ch>
Date: Mon, 17 Jun 2024 22:00:19 +0200
Subject: [PATCH] Fix Mhz -> MHz in Dhrystone benchmark report generation

---
 src/test/scala/vexriscv/DhrystoneBench.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/test/scala/vexriscv/DhrystoneBench.scala b/src/test/scala/vexriscv/DhrystoneBench.scala
index 48d1b67..3fabf42 100644
--- a/src/test/scala/vexriscv/DhrystoneBench.scala
+++ b/src/test/scala/vexriscv/DhrystoneBench.scala
@@ -45,7 +45,7 @@ class DhrystoneBench extends AnyFunSuite {
       val coremarkIterations = intFind.findFirstIn("Iterations       \\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
       val coremarkHzs = intFind.findFirstIn("DCLOCKS_PER_SEC=(\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
       val coremarkPerMhz = 1e6 * coremarkIterations / coremarkTicks
-      report ++= s"$name -> $dmips DMIPS/Mhz $coremarkPerMhz Coremark/Mhz\n"
+      report ++= s"$name -> $dmips DMIPS/MHz $coremarkPerMhz Coremark/MHz\n"
     }
 
   }