From ea7a18c7f40179e71c8389873811a1cf120b8259 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 20 Apr 2022 11:16:19 +0200 Subject: [PATCH] plugin: caches: Fix "Can't resolve the literal value of" Both registers were initialized with unsigned integers without a value. This triggered: [error] Exception in thread "main" spinal.core.SpinalExit: [error] Can't resolve the literal value of (..._rspCounter : UInt[32 bits]) Signed-off-by: Daniel Schultz --- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 +- src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 3fb6498..381f2e0 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -295,7 +295,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, pipeline plug new Area{ //Memory bandwidth counter - val rspCounter = RegInit(UInt(32 bits)) init(0) + val rspCounter = Reg(UInt(32 bits)) init(0) when(dBus.rsp.valid){ rspCounter := rspCounter + 1 } diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 9de1382..035c5dc 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -141,7 +141,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, iBus.cmd.address.allowOverride := cache.io.mem.cmd.address //Memory bandwidth counter - val rspCounter = RegInit(UInt(32 bits)) init(0) + val rspCounter = Reg(UInt(32 bits)) init(0) when(iBus.rsp.valid){ rspCounter := rspCounter + 1 }