From 8abc06c8f27732553f838286a25de0d7040ad672 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Wed, 22 May 2019 17:04:36 +0200
Subject: [PATCH] Add Bmb support for i$/d$

---
 src/main/scala/vexriscv/ip/DataCache.scala    | 38 +++++++++++++++++++
 .../scala/vexriscv/ip/InstructionCache.scala  | 29 ++++++++++++++
 .../vexriscv/plugin/DBusCachedPlugin.scala    |  2 +-
 .../vexriscv/plugin/IBusCachedPlugin.scala    |  2 +-
 4 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 04c84be..d34fceb 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -5,8 +5,10 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared}
 import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
+import spinal.lib.bus.bmb.{Bmb, BmbParameter}
 import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
 import spinal.lib.bus.simple._
+import vexriscv.plugin.DBusSimpleBus
 
 
 case class DataCacheConfig(cacheSize : Int,
@@ -64,6 +66,18 @@ case class DataCacheConfig(cacheSize : Int,
     useBTE = true,
     useCTI = true
   )
+
+  def getBmbParameter() = BmbParameter(
+    addressWidth = 32,
+    dataWidth = 32,
+    lengthWidth = log2Up(this.bytePerLine),
+    sourceWidth = 0,
+    contextWidth = 1,
+    canRead = true,
+    canWrite = true,
+    alignment  = BmbParameter.BurstAlignement.LENGTH,
+    maximumPendingTransactionPerId = Int.MaxValue
+  )
 }
 
 object DataCacheCpuExecute{
@@ -298,6 +312,30 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     bus
   }
 
+
+  def toBmb() : Bmb = {
+    val pipelinedMemoryBusConfig = p.getBmbParameter()
+    val bus = Bmb(pipelinedMemoryBusConfig)
+
+    bus.cmd.valid := cmd.valid
+    bus.cmd.last := cmd.last
+    bus.cmd.context(0) := cmd.wr
+    bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
+    bus.cmd.address := cmd.address.resized
+    bus.cmd.data := cmd.data
+    bus.cmd.length := cmd.length << 2 //TODO better sub word access
+    bus.cmd.mask := cmd.mask
+
+    cmd.ready := bus.cmd.ready
+
+    rsp.valid := bus.rsp.valid && !bus.rsp.context(0)
+    rsp.data  := bus.rsp.data
+    rsp.error := bus.rsp.isError
+    bus.rsp.ready := True
+
+    bus
+  }
+
 }
 
 
diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index e3722d6..1a26dd3 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -5,8 +5,10 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4ReadOnly}
 import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
+import spinal.lib.bus.bmb.{Bmb, BmbParameter}
 import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
 import spinal.lib.bus.simple._
+import vexriscv.plugin.{IBusSimpleBus, IBusSimplePlugin}
 
 
 case class InstructionCacheConfig( cacheSize : Int,
@@ -64,6 +66,18 @@ case class InstructionCacheConfig( cacheSize : Int,
     useBTE = true,
     useCTI = true
   )
+
+  def getBmbParameter() = BmbParameter(
+    addressWidth = 32,
+    dataWidth = 32,
+    lengthWidth = log2Up(this.bytePerLine),
+    sourceWidth = 0,
+    contextWidth = 0,
+    canRead = true,
+    canWrite = false,
+    alignment = BmbParameter.BurstAlignement.LENGTH,
+    maximumPendingTransactionPerId = 1
+  )
 }
 
 
@@ -233,6 +247,21 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
     rsp.error := False //TODO
     bus
   }
+
+  def toBmb() : Bmb = {
+    val busParameter = p.getBmbParameter
+    val bus = Bmb(busParameter)
+    bus.cmd.arbitrationFrom(cmd)
+    bus.cmd.opcode := Bmb.Cmd.Opcode.READ
+    bus.cmd.address := cmd.address.resized
+    bus.cmd.length := (1 << p.bytePerLine) - 1
+    bus.cmd.last := True
+    rsp.valid := bus.rsp.valid
+    rsp.data := bus.rsp.data
+    rsp.error := bus.rsp.isError
+    bus.rsp.ready := True
+    bus
+  }
 }
 
 
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index b8f2ba1..baf9ada 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -18,7 +18,7 @@ class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
   }
 }
 
-class DBusCachedPlugin(config : DataCacheConfig,
+class DBusCachedPlugin(val config : DataCacheConfig,
                        memoryTranslatorPortConfig : Any = null,
                        dBusCmdMasterPipe : Boolean = false,
                        dBusCmdSlavePipe : Boolean = false,
diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index 92722e9..362ac8d 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -31,7 +31,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
                        historyRamSizeLog2 : Int = 10,
                        compressedGen : Boolean = false,
                        keepPcPlus4 : Boolean = false,
-                       config : InstructionCacheConfig,
+                       val config : InstructionCacheConfig,
                        memoryTranslatorPortConfig : Any = null,
                        injectorStage : Boolean = false,
                        withoutInjectorStage : Boolean = false,