diff --git a/README.md b/README.md
index 17a1140..b8a2f36 100644
--- a/README.md
+++ b/README.md
@@ -295,9 +295,9 @@ You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, D
 There is some measurements of Briey SoC timings and area : 
 
 ```
-  Artix 7    -> 231 Mhz 3339 LUT 3533 FF
-  Cyclone V  -> 124 Mhz 2,264 ALMs
-  Cyclone IV -> 124 Mhz 4,709 LUT 3,716 FF
+  Artix 7    -> 239 Mhz 3227 LUT 3410 FF 
+  Cyclone V  -> 125 Mhz 2,207 ALMs
+  Cyclone IV -> 112 Mhz 4,594 LUT 3,620
 ```
 
 ## Murax SoC
@@ -697,7 +697,23 @@ This plugin fit in the fetch stage
 
 #### IBusCachedPlugin
 
-Single way cache implementation, documentation WIP
+Simple and light multi way instruction cache.
+
+| Parameters | type | description |
+| ------ | ----------- | ------ | 
+| cacheSize  | Int | Total storage capacity of the cache |
+| bytePerLine  | Int | Number of byte per cache line  |
+| wayCount  | Int | Number of cache way |
+| twoCycleRam  | Boolean | Check the tags values in the decode stage instead of the fetch stage to relax timings |
+| asyncTagMemory  | Boolean | Read the cache tags in a asyncronus manner instead of syncronous one |
+| addressWidth  | Int | Address width, should be 32 |
+| cpuDataWidth  | Int | Cpu data width, should be 32 |
+| memDataWidth  | Int | Memory data width, could potentialy be something else than 32, but only 32 is currently tested |
+| catchIllegalAccess  | Boolean  | Catch when an memory access is done on non valid memory address (MMU) |
+| catchAccessFault  | Boolean | Catch when the memeory bus is responding with an error  |
+| catchMemoryTranslationMiss  | Boolean  |  Catch when the MMU miss a TLB |
+
+Note : If you enable the twoCycleRam and and the wayCount is bigger than one, then the register file plugin should be configured to read the regFile in a asyncronus manner.
 
 #### DecoderSimplePlugin