From 8c0fbcadacb7070b4268ac97cbc6c4b3eab83146 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sat, 25 Sep 2021 13:18:55 +0200
Subject: [PATCH] Add BrieySim (SpinalSim)

---
 src/main/scala/vexriscv/demo/Briey.scala | 45 +++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
index 709cb23..78d160c 100644
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@@ -9,12 +9,15 @@ import spinal.lib._
 import spinal.lib.bus.amba3.apb._
 import spinal.lib.bus.amba4.axi._
 import spinal.lib.com.jtag.Jtag
+import spinal.lib.com.jtag.sim.JtagTcp
+import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
 import spinal.lib.com.uart.{Apb3UartCtrl, Uart, UartCtrlGenerics, UartCtrlMemoryMappedConfig}
 import spinal.lib.graphic.RgbConfig
 import spinal.lib.graphic.vga.{Axi4VgaCtrl, Axi4VgaCtrlGenerics, Vga}
 import spinal.lib.io.TriStateArray
 import spinal.lib.memory.sdram.SdramGeneration.SDR
 import spinal.lib.memory.sdram._
+import spinal.lib.memory.sdram.sdr.sim.SdramModel
 import spinal.lib.memory.sdram.sdr.{Axi4SharedSdramCtrl, IS42x320D, SdramInterface, SdramTimings}
 import spinal.lib.misc.HexTools
 import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
@@ -160,7 +163,7 @@ object BrieyConfig{
 
 
 
-class Briey(config: BrieyConfig) extends Component{
+class Briey(val config: BrieyConfig) extends Component{
 
   //Legacy constructor
   def this(axiFrequency: HertzNumber) {
@@ -270,6 +273,7 @@ class Briey(config: BrieyConfig) extends Component{
 
 
     val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
+    uartCtrl.io.apb.addAttribute(Verilator.public)
 
 
     val vgaCtrlConfig = Axi4VgaCtrlGenerics(
@@ -443,3 +447,42 @@ object BrieyDe0Nano{
     })
   }
 }
+
+
+
+import spinal.core.sim._
+object BrieySim {
+  def main(args: Array[String]): Unit = {
+    val simSlowDown = false
+    SimConfig.allOptimisation.compile(new Briey(BrieyConfig.default)).doSimUntilVoid{dut =>
+      val mainClkPeriod = (1e12/dut.config.axiFrequency.toDouble).toLong
+      val jtagClkPeriod = mainClkPeriod*4
+      val uartBaudRate = 115200
+      val uartBaudPeriod = (1e12/uartBaudRate).toLong
+
+      val clockDomain = ClockDomain(dut.io.axiClk, dut.io.asyncReset)
+      clockDomain.forkStimulus(mainClkPeriod)
+
+      val tcpJtag = JtagTcp(
+        jtag = dut.io.jtag,
+        jtagClkPeriod = jtagClkPeriod
+      )
+
+      val uartTx = UartDecoder(
+        uartPin = dut.io.uart.txd,
+        baudPeriod = uartBaudPeriod
+      )
+
+      val uartRx = UartEncoder(
+        uartPin = dut.io.uart.rxd,
+        baudPeriod = uartBaudPeriod
+      )
+
+      val sdram = SdramModel(
+        dut.io.sdram,
+        dut.config.sdramLayout,
+        clockDomain
+      )
+    }
+  }
+}