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Fix #412 tightly coupled HAS_SIDE_EFFECT fix

This commit is contained in:
Dolu1990 2024-06-17 10:04:12 +02:00
parent 3ee790d25c
commit 8c191a2824
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -473,7 +473,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
cache.io.cpu.memory.mmuRsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite) cache.io.cpu.memory.mmuRsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite)
if(tightlyGen){ if(tightlyGen){
when(input(MEMORY_TIGHTLY).orR){ when(input(MEMORY_ENABLE) && input(MEMORY_TIGHTLY).orR){
cache.io.cpu.memory.isValid := False cache.io.cpu.memory.isValid := False
input(HAS_SIDE_EFFECT) := False input(HAS_SIDE_EFFECT) := False
} }
@ -585,7 +585,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
insert(MEMORY_LOAD_DATA) := rspShifted insert(MEMORY_LOAD_DATA) := rspShifted
if(tightlyGen){ if(tightlyGen){
when(input(MEMORY_TIGHTLY).orR){ when(input(MEMORY_ENABLE) && input(MEMORY_TIGHTLY).orR){
cache.io.cpu.writeBack.isValid := False cache.io.cpu.writeBack.isValid := False
exceptionBus.valid := False exceptionBus.valid := False
redoBranch.valid := False redoBranch.valid := False