From e4fde184d906d3a5f9b40c2bb51a6756e7a8d324 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 16 Feb 2022 14:12:00 +0100 Subject: [PATCH 01/13] SpinalHDL 1.6.5 --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 19e9c35..11dee63 100644 --- a/build.sbt +++ b/build.sbt @@ -1,4 +1,4 @@ -val spinalVersion = "1.6.3" +val spinalVersion = "1.6.5" lazy val root = (project in file(".")). settings( From e558b795821621d99e8280aa6b877b73182aec33 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 22 Feb 2022 16:15:14 +0100 Subject: [PATCH 02/13] Fix Briey simulation floating rxd blocking the uart #238 --- src/test/cpp/briey/main.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/test/cpp/briey/main.cpp b/src/test/cpp/briey/main.cpp index d2b372c..c0e165a 100644 --- a/src/test/cpp/briey/main.cpp +++ b/src/test/cpp/briey/main.cpp @@ -382,6 +382,8 @@ public: timeProcesses.push_back(asyncReset); timeProcesses.push_back(jtag); timeProcesses.push_back(uartRx); + top->io_uart_rxd = 1; + SdramConfig *sdramConfig = new SdramConfig( 2, //byteCount From 51b8865b66617d09d1363941cbf1c783418c8600 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 18 Mar 2022 12:36:05 +0100 Subject: [PATCH 03/13] Fix VexRiscvSmpClusterGen linux less mhartid --- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index 743d2c2..a0ad2c7 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -206,7 +206,7 @@ object VexRiscvSmpClusterGen { mvendorid = null, marchid = null, mimpid = null, - mhartid = 0, + mhartid = hartId, misaExtensionsInit = 0, misaAccess = CsrAccess.NONE, mtvecAccess = CsrAccess.READ_WRITE, From 9149c420657c7a50f66df4edafc1e6db25c4f478 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Mar 2022 18:53:43 +0100 Subject: [PATCH 04/13] DecoderPlugin now implement forceIllegal API --- src/main/scala/vexriscv/Services.scala | 1 + src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/main/scala/vexriscv/Services.scala b/src/main/scala/vexriscv/Services.scala index 64ce5ae..8a291d6 100644 --- a/src/main/scala/vexriscv/Services.scala +++ b/src/main/scala/vexriscv/Services.scala @@ -24,6 +24,7 @@ trait DecoderService{ def add(key : MaskedLiteral,values : Seq[(Stageable[_ <: BaseType],Any)]) def add(encoding :Seq[(MaskedLiteral,Seq[(Stageable[_ <: BaseType],Any)])]) def addDefault(key : Stageable[_ <: BaseType], value : Any) + def forceIllegal() : Unit } case class ExceptionCause(codeWidth : Int) extends Bundle{ diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index 71e3894..a2ab111 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -71,6 +71,8 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, } } + def forceIllegal() : Unit = if(catchIllegalInstruction) pipeline.decode.input(pipeline.config.LEGAL_INSTRUCTION) := False + val defaults = mutable.LinkedHashMap[Stageable[_ <: BaseType], BaseType]() val encodings = mutable.LinkedHashMap[MaskedLiteral,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]]() var decodeExceptionPort : Flow[ExceptionCause] = null From b2e61caf9e62d8febe59eaf654856edec73e5412 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Mar 2022 18:54:07 +0100 Subject: [PATCH 05/13] CfuPlugin now implement upstream spec --- .../demo/GenSmallAndProductiveCfu.scala | 3 +- .../scala/vexriscv/plugin/CfuPlugin.scala | 47 +++++++++++++++---- 2 files changed, 40 insertions(+), 10 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala b/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala index a571bcc..507b343 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala @@ -53,7 +53,6 @@ object GenSmallAndProductiveCfu extends App{ new CfuPlugin( stageCount = 1, allowZeroLatency = true, - cfuIndexWidth = 4, encodings = List( CfuPluginEncoding ( instruction = M"-------------------------0001011", @@ -64,7 +63,7 @@ object GenSmallAndProductiveCfu extends App{ busParameter = CfuBusParameter( CFU_VERSION = 0, CFU_INTERFACE_ID_W = 0, - CFU_FUNCTION_ID_W = 7, + CFU_FUNCTION_ID_W = 3, CFU_REORDER_ID_W = 0, CFU_REQ_RESP_ID_W = 0, CFU_INPUTS = 2, diff --git a/src/main/scala/vexriscv/plugin/CfuPlugin.scala b/src/main/scala/vexriscv/plugin/CfuPlugin.scala index b8e98cb..de6daa1 100644 --- a/src/main/scala/vexriscv/plugin/CfuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CfuPlugin.scala @@ -23,6 +23,7 @@ case class CfuPluginParameter( case class CfuBusParameter(CFU_VERSION : Int = 0, CFU_INTERFACE_ID_W : Int = 0, CFU_FUNCTION_ID_W : Int, + CFU_CFU_ID_W : Int = 0, CFU_REORDER_ID_W : Int = 0, CFU_REQ_RESP_ID_W : Int = 0, CFU_STATE_INDEX_NUM : Int = 0, @@ -31,7 +32,9 @@ case class CfuBusParameter(CFU_VERSION : Int = 0, CFU_OUTPUTS : Int, CFU_OUTPUT_DATA_W : Int, CFU_FLOW_REQ_READY_ALWAYS : Boolean, - CFU_FLOW_RESP_READY_ALWAYS : Boolean) + CFU_FLOW_RESP_READY_ALWAYS : Boolean, + CFU_WITH_STATUS : Boolean = false, + CFU_RAW_INSN_W : Int = 0) case class CfuCmd( p : CfuBusParameter ) extends Bundle{ val function_id = UInt(p.CFU_FUNCTION_ID_W bits) @@ -39,6 +42,8 @@ case class CfuCmd( p : CfuBusParameter ) extends Bundle{ val request_id = UInt(p.CFU_REQ_RESP_ID_W bits) val inputs = Vec(Bits(p.CFU_INPUT_DATA_W bits), p.CFU_INPUTS) val state_index = UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits) + val cfu_index = UInt(p.CFU_CFU_ID_W bits) + val raw_insn = Bits(p.CFU_RAW_INSN_W bits) def weakAssignFrom(m : CfuCmd): Unit ={ def s = this WeakConnector(m, s, m.function_id, s.function_id, defaultValue = null, allowUpSize = false, allowDownSize = true , allowDrop = true) @@ -51,6 +56,7 @@ case class CfuCmd( p : CfuBusParameter ) extends Bundle{ case class CfuRsp(p : CfuBusParameter) extends Bundle{ val response_id = UInt(p.CFU_REQ_RESP_ID_W bits) val outputs = Vec(Bits(p.CFU_OUTPUT_DATA_W bits), p.CFU_OUTPUTS) + val status = p.CFU_WITH_STATUS generate Bits(3 bits) def weakAssignFrom(m : CfuRsp): Unit ={ def s = this @@ -95,7 +101,7 @@ class CfuPlugin(val stageCount : Int, val busParameter : CfuBusParameter, val encodings : List[CfuPluginEncoding] = null, val stateAndIndexCsrOffset : Int = 0xBC0, - val cfuIndexWidth : Int = 0) extends Plugin[VexRiscv]{ + val statusCsrOffset : Int = 0x801) extends Plugin[VexRiscv]{ def p = busParameter assert(p.CFU_INPUTS <= 2) @@ -151,18 +157,33 @@ class CfuPlugin(val stageCount : Int, import pipeline.config._ val csr = pipeline plug new Area{ + val factory = pipeline.service(classOf[CsrInterface]) + val en = Reg(Bool()) init(False) + factory.rw(stateAndIndexCsrOffset, 31, en) + val stateId = Reg(UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits)) init(0) if(p.CFU_STATE_INDEX_NUM > 1) { assert(stateAndIndexCsrOffset != -1, "CfuPlugin stateCsrIndex need to be set in the parameters") - pipeline.service(classOf[CsrInterface]).rw(stateAndIndexCsrOffset, 16, stateId) + factory.rw(stateAndIndexCsrOffset, 16, stateId) } - bus.cmd.state_index := stateId - val cfuIndex = Reg(UInt(cfuIndexWidth bits)) init(0) - if(cfuIndexWidth != 0){ - pipeline.service(classOf[CsrInterface]).rw(stateAndIndexCsrOffset, 0, cfuIndex) + + val cfuIndex = Reg(UInt(p.CFU_CFU_ID_W bits)) init(0) + if(p.CFU_CFU_ID_W != 0){ + factory.rw(stateAndIndexCsrOffset, 0, cfuIndex) + } + val status = p.CFU_WITH_STATUS generate new Area{ + val CU, OP, FI, OF, SI, CI = RegInit(False) + val flags = List(CU, OP, FI, OF, SI, CI).reverse + factory.rw(statusCsrOffset, flags.zipWithIndex.map(_.swap) :_*) + factory.duringWrite(statusCsrOffset){ + decode.arbitration.haltByOther := True //Handle CSRW to decode + } } } + when(decode.input(CFU_ENABLE) && !csr.en){ + pipeline.service(classOf[DecoderService]).forceIllegal() + } forkStage plug new Area{ import forkStage._ @@ -181,9 +202,12 @@ class CfuPlugin(val stageCount : Int, // bus.cmd.function_id := U(input(INSTRUCTION)(14 downto 12)).resized val functionIdFromInstructinoWidth = encodings.map(_.functionIdWidth).max val functionsIds = encodings.map(e => U(Cat(e.functionId.map(r => input(INSTRUCTION)(r))), functionIdFromInstructinoWidth bits)) - bus.cmd.function_id := csr.cfuIndex @@ functionsIds.read(input(CFU_ENCODING)) + bus.cmd.cfu_index := csr.cfuIndex + bus.cmd.state_index := csr.stateId + bus.cmd.function_id := functionsIds.read(input(CFU_ENCODING)) bus.cmd.reorder_id := 0 bus.cmd.request_id := 0 + bus.cmd.raw_insn := input(INSTRUCTION).resized if(p.CFU_INPUTS >= 1) bus.cmd.inputs(0) := input(RS1) if(p.CFU_INPUTS >= 2) bus.cmd.inputs(1) := input(CFU_INPUT_2_KIND).mux( CfuPlugin.Input2Kind.RS -> input(RS2), @@ -212,6 +236,13 @@ class CfuPlugin(val stageCount : Int, arbitration.haltItself setWhen(!rsp.valid) rsp.ready := !arbitration.isStuckByOthers output(REGFILE_WRITE_DATA) := rsp.outputs(0) + if(p.CFU_WITH_STATUS) when(arbitration.isFiring){ + switch(rsp.status) { + for (i <- 1 to 6) is(i) { + csr.status.flags(i-1) := True + } + } + } } } From 5dc91a8be484e5f9acd70e11ac6d042cc04759ea Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Mar 2022 18:54:18 +0100 Subject: [PATCH 06/13] Add MuraxCfu --- src/main/scala/vexriscv/demo/Murax.scala | 48 ++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 7c679a1..95a35b5 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -335,6 +335,54 @@ object Murax{ } } +object MuraxCfu{ + def main(args: Array[String]) { + SpinalVerilog{ + val config = MuraxConfig.default + config.cpuPlugins += new CfuPlugin( + stageCount = 1, + allowZeroLatency = true, + encodings = List( + CfuPluginEncoding ( + instruction = M"-------------------------0001011", + functionId = List(14 downto 12), + input2Kind = CfuPlugin.Input2Kind.RS + ) + ), + busParameter = CfuBusParameter( + CFU_VERSION = 0, + CFU_INTERFACE_ID_W = 0, + CFU_FUNCTION_ID_W = 3, + CFU_REORDER_ID_W = 0, + CFU_REQ_RESP_ID_W = 0, + CFU_INPUTS = 2, + CFU_INPUT_DATA_W = 32, + CFU_OUTPUTS = 1, + CFU_OUTPUT_DATA_W = 32, + CFU_FLOW_REQ_READY_ALWAYS = false, + CFU_FLOW_RESP_READY_ALWAYS = false, + CFU_WITH_STATUS = true, + CFU_RAW_INSN_W = 32, + CFU_CFU_ID_W = 4, + CFU_STATE_INDEX_NUM = 5 + ) + ) + + val toplevel = Murax(config) + + toplevel.rework { + for (plugin <- toplevel.system.cpu.plugins) plugin match { + case plugin: CfuPlugin => plugin.bus.toIo().setName("miaou") + case _ => + } + } + + toplevel + } + } +} + + object Murax_iCE40_hx8k_breakout_board_xip{ case class SB_GB() extends BlackBox{ From 4bddb091aef6fb527e9843449a6f3b44d66042ef Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Mar 2022 18:58:18 +0100 Subject: [PATCH 07/13] Update CFU example --- .../scala/vexriscv/demo/GenSmallAndProductiveCfu.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala b/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala index 507b343..d28e318 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndProductiveCfu.scala @@ -70,9 +70,12 @@ object GenSmallAndProductiveCfu extends App{ CFU_INPUT_DATA_W = 32, CFU_OUTPUTS = 1, CFU_OUTPUT_DATA_W = 32, - CFU_STATE_INDEX_NUM = 5, CFU_FLOW_REQ_READY_ALWAYS = false, - CFU_FLOW_RESP_READY_ALWAYS = false + CFU_FLOW_RESP_READY_ALWAYS = false, + CFU_WITH_STATUS = true, + CFU_RAW_INSN_W = 32, + CFU_CFU_ID_W = 4, + CFU_STATE_INDEX_NUM = 5 ) ), new YamlPlugin("cpu0.yaml") From ccff48f872a7948335accff10f406f8b2eb4d200 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 30 Mar 2022 16:17:57 +0200 Subject: [PATCH 08/13] deprecated Data.keep --- src/main/scala/vexriscv/VexRiscv.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index d3feda3..ed7e37e 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -136,10 +136,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ plugins ++= config.plugins //regression usage - val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)).keep().addAttribute (Verilator.public) - val lastStagePc = CombInit(stages.last.input(config.PC)).keep().addAttribute(Verilator.public) - val lastStageIsValid = CombInit(stages.last.arbitration.isValid).keep().addAttribute(Verilator.public) - val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring).keep().addAttribute(Verilator.public) + val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)).dontSimplifyIt().addAttribute (Verilator.public) + val lastStagePc = CombInit(stages.last.input(config.PC)).dontSimplifyIt().addAttribute(Verilator.public) + val lastStageIsValid = CombInit(stages.last.arbitration.isValid).dontSimplifyIt().addAttribute(Verilator.public) + val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring).dontSimplifyIt().addAttribute(Verilator.public) //Verilator perf decode.arbitration.removeIt.noBackendCombMerge From 2d2017465e4923b91e4e7752e1ca5e890eebb2b6 Mon Sep 17 00:00:00 2001 From: Andreas Wallner Date: Sat, 2 Apr 2022 18:22:10 +0200 Subject: [PATCH 09/13] Fix reset vector of GenCustomSimdAdd With the old reset vector half of the tests fail since they expect the CPU to start at 0x80000000. (e.g. I-IO, I-NOP, I-LUI, etc.) --- src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala | 2 +- src/test/cpp/custom/simd_add/src/ld | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala index 8b137f5..8d9d6be 100644 --- a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala +++ b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala @@ -13,7 +13,7 @@ object GenCustomSimdAdd extends App{ plugins = List( new SimdAddPlugin, new IBusSimplePlugin( - resetVector = 0x00000000l, + resetVector = 0x80000000l, cmdForkOnSecondStage = false, cmdForkPersistence = false, prediction = NONE, diff --git a/src/test/cpp/custom/simd_add/src/ld b/src/test/cpp/custom/simd_add/src/ld index 8d95523..3a4f112 100644 --- a/src/test/cpp/custom/simd_add/src/ld +++ b/src/test/cpp/custom/simd_add/src/ld @@ -1,13 +1,11 @@ OUTPUT_ARCH( "riscv" ) MEMORY { - onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 8K } SECTIONS { - . = 0x000; - .crt_section : { . = ALIGN(4); From db3403359372289bd2387e1f92baa31abde5a952 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 8 Apr 2022 11:09:07 +0200 Subject: [PATCH 10/13] #240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++++ src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala | 3 +++ 2 files changed, 7 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index bd48928..5ba1523 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -532,6 +532,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep override def setup(pipeline: VexRiscv): Unit = { import pipeline.config._ + if(!config.ebreakGen) { + SpinalWarning("This VexRiscv configuration is set without software ebreak instruction support. Some software may rely on it (ex: Rust). (This isn't related to JTAG ebreak)") + } + csrMapping = new CsrMapping() inWfi = False.addTag(Verilator.public) diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index a2ab111..a525b77 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -79,6 +79,9 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, override def setup(pipeline: VexRiscv): Unit = { + if(!catchIllegalInstruction) { + SpinalWarning("This VexRiscv configuration is set without illegal instruction catch support. Some software may rely on it (ex: Rust)") + } if(catchIllegalInstruction) { val exceptionService = pipeline.plugins.filter(_.isInstanceOf[ExceptionService]).head.asInstanceOf[ExceptionService] decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode).setName("decodeExceptionPort") From 3b8270b82bfbdba29e98498e483847253888b2fc Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 11 Apr 2022 11:59:41 +0200 Subject: [PATCH 11/13] #241 Fix Murax/Briey TB timeouts --- src/test/cpp/briey/main.cpp | 2 -- src/test/cpp/common/framework.h | 7 +++++-- src/test/cpp/murax/main.cpp | 4 +--- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/test/cpp/briey/main.cpp b/src/test/cpp/briey/main.cpp index c0e165a..bebe880 100644 --- a/src/test/cpp/briey/main.cpp +++ b/src/test/cpp/briey/main.cpp @@ -466,8 +466,6 @@ int main(int argc, char **argv, char **env) { uint64_t duration = timer_end(startedAt); cout << endl << "****************************************************************" << endl; - cout << "Had simulate " << workspaceCycles << " clock cycles in " << duration*1e-9 << " s (" << workspaceCycles / (duration*1e-9) << " Khz)" << endl; - cout << "****************************************************************" << endl << endl; exit(0); diff --git a/src/test/cpp/common/framework.h b/src/test/cpp/common/framework.h index 42c1f34..ed419ad 100644 --- a/src/test/cpp/common/framework.h +++ b/src/test/cpp/common/framework.h @@ -127,7 +127,6 @@ public: class success : public std::exception { }; -static uint32_t workspaceCycles = 0; template class Workspace{ public: @@ -180,7 +179,7 @@ public: #endif } - Workspace* run(uint32_t timeout = 5000){ + Workspace* run(double timeout = 1e6){ // init trace dump #ifdef TRACE @@ -205,6 +204,10 @@ public: if(p->wakeEnable && p->wakeDelay < delay) delay = p->wakeDelay; + if(time*timeToSec > timeout){ + printf("Simulation timeout triggered (%f)\n", time*timeToSec); + fail(); + } if(delay == ~0l){ fail(); } diff --git a/src/test/cpp/murax/main.cpp b/src/test/cpp/murax/main.cpp index 9738e84..735875f 100644 --- a/src/test/cpp/murax/main.cpp +++ b/src/test/cpp/murax/main.cpp @@ -54,12 +54,10 @@ int main(int argc, char **argv, char **env) { printf("BOOT\n"); timespec startedAt = timer_start(); - MuraxWorkspace().run(100e6); + MuraxWorkspace().run(1e9); uint64_t duration = timer_end(startedAt); cout << endl << "****************************************************************" << endl; - cout << "Had simulate " << workspaceCycles << " clock cycles in " << duration*1e-9 << " s (" << workspaceCycles / (duration*1e-9) << " Khz)" << endl; - cout << "****************************************************************" << endl << endl; exit(0); From ea7a18c7f40179e71c8389873811a1cf120b8259 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 20 Apr 2022 11:16:19 +0200 Subject: [PATCH 12/13] plugin: caches: Fix "Can't resolve the literal value of" Both registers were initialized with unsigned integers without a value. This triggered: [error] Exception in thread "main" spinal.core.SpinalExit: [error] Can't resolve the literal value of (..._rspCounter : UInt[32 bits]) Signed-off-by: Daniel Schultz --- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 +- src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 3fb6498..381f2e0 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -295,7 +295,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, pipeline plug new Area{ //Memory bandwidth counter - val rspCounter = RegInit(UInt(32 bits)) init(0) + val rspCounter = Reg(UInt(32 bits)) init(0) when(dBus.rsp.valid){ rspCounter := rspCounter + 1 } diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 9de1382..035c5dc 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -141,7 +141,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, iBus.cmd.address.allowOverride := cache.io.mem.cmd.address //Memory bandwidth counter - val rspCounter = RegInit(UInt(32 bits)) init(0) + val rspCounter = Reg(UInt(32 bits)) init(0) when(iBus.rsp.valid){ rspCounter := rspCounter + 1 } From 9506b0b8f1965782600170a63bcacc52a4016487 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 29 Apr 2022 14:16:41 +0200 Subject: [PATCH 13/13] SpianlHDL 1.7.0 --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 11dee63..6e58704 100644 --- a/build.sbt +++ b/build.sbt @@ -1,4 +1,4 @@ -val spinalVersion = "1.6.5" +val spinalVersion = "1.7.0" lazy val root = (project in file(".")). settings(