From dcdfa79024f5c6b88c04eadfd3140dc3733a33a1 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 3 Jan 2019 20:07:38 +0100 Subject: [PATCH 1/3] fix run-main into runMain --- README.md | 14 +++++++------- scripts/Murax/iCE40-hx8k_breakout_board/Makefile | 4 ++-- .../Murax/iCE40-hx8k_breakout_board_xip/Makefile | 4 ++-- scripts/Murax/iCE40HX8K-EVB/Makefile | 4 ++-- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/README.md b/README.md index 430d162..ef6df53 100644 --- a/README.md +++ b/README.md @@ -162,13 +162,13 @@ You can find two example CPU instances in: To generate the corresponding RTL as a VexRiscv.v file, run the following commands in the root directory of this repository: ```sh -sbt "run-main vexriscv.demo.GenFull" +sbt "runMain vexriscv.demo.GenFull" ``` or ```sh -sbt "run-main vexriscv.demo.GenSmallest" +sbt "runMain vexriscv.demo.GenSmallest" ``` NOTES: @@ -204,7 +204,7 @@ Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a ```sh #in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself => -sbt "run-main vexriscv.demo.GenFull" +sbt "runMain vexriscv.demo.GenFull" cd src/test/cpp/regression make run DEBUG_PLUGIN_EXTERNAL=yes @@ -254,7 +254,7 @@ the [Pinsec SOC](https://spinalhdl.github.io/SpinalDoc/spinal/lib/pinsec/hardwar To generate the Briey SoC Hardware: ```sh -sbt "run-main vexriscv.demo.Briey" +sbt "runMain vexriscv.demo.Briey" ``` To run the verilator simulation of the Briey SoC which can then be connected to OpenOCD/GDB, first get those dependencies: @@ -309,10 +309,10 @@ To generate the Murax SoC Hardware : ```sh # To generate the SoC without any content in the ram -sbt "run-main vexriscv.demo.Murax" +sbt "runMain vexriscv.demo.Murax" # To generate the SoC with a demo program already in ram -sbt "run-main vexriscv.demo.MuraxWithRamInit" +sbt "runMain vexriscv.demo.MuraxWithRamInit" ``` The demo program included by default with `MuraxWithRamInit` will blink the @@ -560,7 +560,7 @@ and is self-tested by the `src/test/cpp/custom/simd_add` application by running ```sh # Generate the CPU -sbt "run-main vexriscv.demo.GenCustomSimdAdd" +sbt "runMain vexriscv.demo.GenCustomSimdAdd" cd src/test/cpp/regression/ diff --git a/scripts/Murax/iCE40-hx8k_breakout_board/Makefile b/scripts/Murax/iCE40-hx8k_breakout_board/Makefile index 078af3b..4689674 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board/Makefile +++ b/scripts/Murax/iCE40-hx8k_breakout_board/Makefile @@ -3,10 +3,10 @@ VERILOG = ../../../Murax.v toplevel.v generate : - (cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit") + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") ../../../Murax.v : - (cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit") + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") ../../../Murax.v*.bin: diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile index ca74503..88aa1a2 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile @@ -3,10 +3,10 @@ VERILOG = ../../../Murax_iCE40_hx8k_breakout_board_xip.v generate : - #(cd ../../..; sbt "run-main vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip") + #(cd ../../..; sbt "runMain vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip") ../../../Murax_iCE40_hx8k_breakout_board_xip.v : - #(cd ../../..; sbt "run-main vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip") + #(cd ../../..; sbt "runMain vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip") ../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin: diff --git a/scripts/Murax/iCE40HX8K-EVB/Makefile b/scripts/Murax/iCE40HX8K-EVB/Makefile index e69f58c..e90ed02 100644 --- a/scripts/Murax/iCE40HX8K-EVB/Makefile +++ b/scripts/Murax/iCE40HX8K-EVB/Makefile @@ -3,10 +3,10 @@ VERILOG = ../../../Murax.v toplevel.v toplevel_pll.v generate : - (cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit") + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") ../../../Murax.v : - (cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit") + (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") ../../../Murax.v*.bin: From f4f854ae4f8a953baaa04b981fd39b322dff5edb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 14 Jan 2019 13:32:16 +0100 Subject: [PATCH 2/3] SpinalHDL 1.3.1 --- build.sbt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 3075bba..3c2aae6 100644 --- a/build.sbt +++ b/build.sbt @@ -29,8 +29,8 @@ lazy val root = (project in file(".")). version := "1.0.0" )), libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.0", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.0", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.1", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.1", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" ), From b5caca54cd97e968f8b6c7494aa8aed7388a23c6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 16 Jan 2019 15:25:50 +0100 Subject: [PATCH 3/3] restore all feature in TestsWorkspace --- src/main/scala/vexriscv/TestsWorkspace.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 93d494f..34d047d 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -153,7 +153,7 @@ object TestsWorkspace { // wfiGenAsNop = true, // ucycleAccess = CsrAccess.NONE // )), -// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = true, catchAddressMisaligned = true,